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Antenna Interface Module in the Embedded Processor TMS320C6474

About This Page

This manual was designed for both beginners and advanced users of TI of the Antenna Interface in the embedded processor TMS320C6474 software library. It is intended to be the reference guide for the understanding of the architecture of the library, as well as the programming concepts on top of which the software is built.

About Antenna Interface

Note: AIF Example code for C6474-IDT is available on TI's Gforge : https://gforge.ti.com/gf/project/c6474aif/

The embedded processor TMS320C6474 is in reality a high-performance system-on-a-chip (SoC) used for the WCDMA-FDD infrastructure baseband solution. Its architecture includes the MAC, symbol rate, transmit and receive chip rate, the chip rate assist as well as the antenna interface functionality. Owing to this architecture, users may develop their own WCDMA-FDD modem design. Antenna Interface (AIF) module consists of six high-speed serial (SERDES) links, compliant to OBSAI-RP3 and CPRI protocols. This module is capable of up to 3.072 Gbps operation per link. However, IQ stream data transfers studies during the internship only restricted to the implementation on CPRI 2.0. AIF module is primarily used for user plane data transfers between uplink and downlink baseband embedded processors and a high speed serial interface. Figure below shows an overview of the AIF module:

The AIF module is connected to the embedded processor cores via the DMA switch fabric through vbus interface for the internal connection. The external connection to RF units or other TMS320C6474 units is achievable with SERDES links.

User Plane Data

User plane data are data from radio base station to the mobile station and vice versa. These data are transferred in the form of IQ data. With CPRI mode, the IQ sample width is formed of:

between 4 and 20 bits (in the form of 4, 8, 10 or 20 bits) for uplink data
between 8 and 20 bits (in the form of 8 or 20 bits) for downlink data

However, only a combination of 8/16 is allowed when using the AIF module. In addition, CPRI allows oversampling of IQ data, which is useful for noise reduction:

oversampling factor of 2 or 4 is assumed for UTRA FDD in uplink
oversampling factor of 1 or 2 is assumed for UTRA FDD in downlink

At the moment, only the combination of 2/1 oversampling factor is available with AIF module. Downlink data are data sent to the external interface (from REC to RE for a logical connection), whereas uplink data are the ones received from the external interface (from RE to REC for a logical connection):

Example of an AIF application

An example of AIF application is its utilization for data transfers between RF cards and a baseband system for data processing. Besides that, AIF is also used for the inter-TMS30C6474 control data transfer (or control data to/from the RF units). By means of AIF module, user may directly drive CPRI backplanes.

Common Public Radio Interface (CPRI) Protocol

Main Article: CPRI Protocol

The Common Public Radio Interface (CPRI) protocol consists of a specification that enables flexible and efficient product differentiation for radio base stations and independent technology evolution for RE and REC. In other word, the goal of CPRI is to allow base stations manufacturers to share a common protocol and more easily adapt platforms from one customer to the other. Besides that, CPRI focuses on simplified radio base station architecture by dividing the radio base station into a radio and a control part, by specifying one new interface. The groups cooperating on defining CPRI specifications are Ericsson AB, Huawei Technologies Co. Ltd, NEC Corporation, Nortel Networks Ltd, Alcatel Lucent and Nokia Siemens Networks GmbH & Co. KG.

AIF Module in TMS320C6474

The role of AIF module is to convert serial data flowing on the backplane to byte format data. This data is captured and stored in the data buffer RAM. SERDES links can carry two type of data; circuit-switched data and packet-switched data. However, only the former type is used in CPRI mode. Besides that, AIF can also perform combining/de-combining (for OBSAI RP3 only), aggregation of an inbound link with an outbound link, as well as redirection of inbound link(s) to a specific outbound link(s).

This peripheral uses 8b/10b encoding/decoding at the Tx/Rx MAC for serial transmission over the interface. It also supports over sample ratios (1x for downlink and up to 2x for uplink), link redirection, and multiple loopback test modes besides data tracing as well as clock stop and emulation.

Sub-module	Description
Serializer/De-Serializer links (SERDES)	Two SERDES macros available; one has four while the other has two links with a SERDES reference clock for each macro. The receiver SERDES (Rx SERDES) converts serial binary data into 10 bit clocks while the transmitter SERDES (Tx SerDES) converts 10 bit clocks into serial stream.
Rx MAC	Performs 8b/10b decoding and moves data from the BYTE_CLK domain to VBUS_CLK domain. It also performs pi offset measurement
Tx MAC	Performs 8b/10b encoding and moves data from the VBUS_CLK domain to BYTE_CLK domain. It also creates the frame structure based on the programmed link rate.
CPRI input data format convert (Rx Protocol Translator)	De-interleaves the alternating IQ data bit
CPRI output data format convert (Tx Protocol Translator)	Interleaves the alternating IQ data bit
Combiner/De-combiner	Combines from one to four slower links into a single faster link (only available in OBSAI RP3 mode) and vice versa.
Aggregator	Sums IQ data from different sources (if needed), as well as adding control words to form 16 words in CPRI mode
CPRI Protocol Decoder	Extract AxC messages from byte stream and stores the payload data in the data buffer RAM.
CPRI Protocol Encoder	Synchronizes messages and frame construction with byte stream, as well as read appropriate payload data from data buffer RAM.
Data buffer RAM	Stores IQ and control data
VBUSP DMA bus interface (slave)	Separate read-only and write-only 128-bit interfaces between the AIF and DMA switch fabric and transfers the data with a high data rate.
VBUSP configuration bus interface (slave)	32-bit interface between the AIF and configuration switch fabric. It transfers the low data rate data such as configuration and status information data.
Exception event handler	Aggregates a large number of errors/alarms from AIF to multiple system events used as DSP interrupts and triggers for data tracing

Maximum number of Antenna Carriers in CPRI

The external AIF interface that connects the AIF module and RF units and other embedded processor units is done using SERDES interface which constitutes of six SERDES links. These serial links support 1x, 2x and 4x link rates with independent rates per link in CPRI mode. Each link format can support until a fix number of antenna carriers (AxC) with an average rate of:

Link Rate	Line Rate	Data Rate	Max. no. of AxC for 8 UL/16 DL bit
1x	614.4 Mbps	491.52 Mbps	3
2x	1.2288 Gbps(2 x 614.4 Mbps)	983.04 Mbps	7
4x	2.4576 Gbps(2 x 1.2288 Gbps)	1.96608 Gbps	15

AIF Data Flow

See Main Article: AIF Data Flow

AIF module setup

See Main Article: AIF Module Setup

CPRI Transmission chain with AIF Module

Introduction

The AIF module interoperability test consists of a transmission chain in CPRI protocol. Its contents:

The AIF module of the embedded TMS320C6474, for IQ downlink/uplink data processing.

A CPRI – TDM, used for:

Downlink data transformation to time division multiplexing form before sending the IQ data simultaneously into a digital-to-analog converter.

Time division de-multiplexing data; data fetched from an analog-to-digital converter are transformed to a CPRI data format before sending them to the AIF module in the TMS320C6474.

A digital-to-analog converter; digital downlink data from the embedded processor are converted analogically.
An IQ modulator for data modulation before downlink data are sent in the air.
An IQ de-modulator, to de-modulate data fetched from a receptor antenna.
An analog-to-digital converter for data conversion; analog data coming from the IQ de-modulator are converted before it is sent to the AIF module.

The transmission line is represented by:

Dual TMS320C6474 AMC Mezzanine board; source of the AIF module for downlink/uplink data processing.
CPRI™ – TDM FIC EVM board; it allows a Time-Division Multiplexing (TDM), as well as Time-Division De-Multiplexing CPRI solution from a radio equipment controller to radio equipment(s). The advantage of using this platform is its possibilities of connecting to the embedded processor for data processing through CPRI links directly.
TSW3003 demonstration kit, which contains four Texas Ins.\’s components:
1. CDCM7005 clock distribution chip, used to generate and synchronize the clock outputs to the system. The device has five outputs which can be either LVPECL or LVCMOS, and can be divided down by 1, 2, 3, 4, 6, 8 and 16.
2. DAC5687, a 16-bit interpolating dual digital-to-analog converter (DAC). It incorporates a digital modulator, independent differential offset control, and IQ amplitude control. This device is mostly used in baseband mode or in low IF mode with an analog quadrature modulator.
3. TRF3703, a direct up-conversion IQ modulator. It accepts a differential input voltage quadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the LO drive frequency.
4. TRF3761, highly integrated frequency synthesizers, optimized for wireless infrastructure applications. It includes an integrated VCO and integer-N PLL.
TRF3710, a highly linear and integrated direct-conversion quadrature de-modulator optimized for third-generation wireless infrastructure. The TRF3710 integrates balanced I and Q mixers, LO buffers, and phase splitters to convert an RF signal directly to I and Q baseband.
ADS5231, a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter (ADC).

Dual TMS320C6474 AMC Mezzanine board

See Main Article: Dual TMS320C6474 AMC Mezzanine board

CPRI™ – TDM FIC EVM board

See Main Article: CPRI™ – TDM FIC EVM board

TSW3003 demonstration kit

See Article: TSW3003 demonstration kit

IQ de-modulator, TRF3710

See Article: TRF3710

Analog-to-digital converter, ADS5231

The ADS5231 EVM is a platform for Analog-to-Digital Converter (ADC) ADS5231, which is a dual, high-speed, high dynamic range, 12-bit pipelined ADC. This platform is powered with a 3.3 V from a DC power supply through J11 and return to J10 for analog supply, and through J17 and return to J18 for output buffer supply. Its clock frequency range varies from 20 MHz to 40 MHz with the presence of PLL. As mentioned in the previous section, the source clock for this ADC is 30.72 MHz, which is derived from TSW3003 kit, owing to the CDCM7005 clock distribution chip. IQ data coming from the IQ de-modulator enter the ADC via external SMA connectors, AINA_TRF (J15) and AINB_TRF (J16). Once converted, digital outputs of 12 bit resolution are available via two 40-pin connectors; J8 and J21. This uplink data is then sent to the CPRI™ - TDM FIC EVM for data transmission to the embedded processor.

Board connection

The screenshot below shows the connection between devices:

Description	Connection
Dual TMS320C6474 AMC Mezzanine board to CPRI™ – TDM FIC EVM board	AMC connector (J9)
CPRI™ – TDM FIC EVM board to TSW3003 kit	-J100 to channel A of TSW3003 -CPRI™ – TDM clock (J15) to EXT_REF_CLK (J35) of TSW3003 -Output clock to ADS5231: J8 to J3 (ADCLK) -Output data to input RF in the IQ de- modulator for closed loop system: REFOUT(J32) to RFIN(J6)
TRF3710 to ADS5231	-I data (J3) to AINA_TRF(J15) -Q data (J10) to AINB_TRF(J16)
TSW3003 (used for LO only) to TRF3710	RF_OUT(J32) to LO_P(J7)

Test and Verification

Open loop system

For an open loop system configuration, the embedded processor plays two roles:

A baseband system (Transmission part, Tx)

- The processor sends numerical IQ data represented by a WCDMA-FDD pattern to the CPRI link via AIF module.

- The EVM board is connected to a CPRI™-TDM device via an AMC connector; data are sent to the CPRI link is to be found in the CPRI™-TDM device. Once the data are multiplexed, these data are sent to TSW3003 for digital-to-analog conversion (DAC5687). Once converted, these data are modulated using an IQ modulator (TRF 3703) before they are sent to radio equipments.

The signal sent to radio equipments is observed using a spectrum analyzer:

A radio equipment (Reception part, Rx)

- Initially, data received from an antenna are demodulated owing to IQ de- modulator (TRF 3710).

These data are next converted to digital data using an ADC before they are sent to the CPRI link via the CPRI™-TDM device.

The data coming from the CPRI link are stored in the processor.

Closed loop system

In the close loop system, firstly the embedded processor acts as a baseband system. However, instead of sending the data to radio equipments, data are sent directly to an IQ de-modulator in the reception side. Playing the role as the radio equipment on the reception side, and furthermore, since the signal is centered and symmetrical, it is sufficient to observe only half of the frequency spectrum to validate the pattern received. Below is the figure observed in the Code Composer Studio, corresponds to the WCDMA-FDD pattern received by the processor: