AM/DM37x Overview

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Important Documentation

Block Diagram

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Product Matrix

For help selecting a processor, please look at the DSP & ARM MPU Selection Tool.

Refer to the OMAP35x To AM37x Hardware Migration Guide for a comparison between the OMAP35x and AM/DM37x devices.

These devices come in different speed grades and temperature ratings described by part number. For details on the nomenclature of the device part number, please refer to the "Device Support" section of the corresponding data-sheet.


DM3730 DM3725 AM3715 AM3703
IVA2.2 Subsystem Yes Yes No No
2D/3D Graphics Accelerator Yes No Yes No

OMAP35x to AM/DM37x Migration Guide

Silicon/HW Design Reference Documents

Board Design Guidelines

Power Reference Design

Design in Guide for TPS65023

Design in Guide for TPS65073

TPS65910 User Guide

AM/DM37x PMIC Comparison

  • Check the latest PMU flyer from our Power Management group
Feature TPS65950 TPS65951 TPS65930 TPS65920 TPS65921 TPS65910 TPS65023 TPS65073
Integrated Battery Charger AC/USB USB AC recognition No No Battery charger detection function available No No Power Path Management AC/USB
Audio Codec and Drivers 5 Stereo TX 2 Stereo RX 4 Stereo TX 4 Stereo RX 1 Stereo TX 1 Stereo RX No No No No No
USB 2.0 HS PHY Yes Yes, with USB protection integrated Yes Yes Yes No No No
OTG VBUS supply 100mA 100mA 100mA 100mA 100mA 100mA No No
Drivers RGB and Vibrator RGB and Vibrator RGB or Vibrator RGB or Vibrator No 10mA LED Driver No No
Keypad Interface 8x8 No 6x6 6x6 8x8 No No No
RTC 32KHz needs external 32KHz needs external 32KHz needs external 32KHz needs external 32KHz 32KHz can be generated from HF clock needs external 32KHz No No
10-bit ADC 8 inputs 8 inputs 3 inputs 2 inputs 2 inputs No No No
VDD1 Max Current 1.2A (A3 version 1.4A) 1.4A 1.2A 1.2A 1.4A 1.5A 1.5A 1.5A
Power 3 DCDC 10 LDOs 3 DCDC 8 LDOs 3 DCDC 4 LDOs 3 DCDC 4 LDOs 3 DCDC 4 LDOs 3 DCDC 9 LDOs 1x 5V Boost 3 DCDC 2 LDO 3 DCDC 2 LDO
SmartReflex Class3 Class3 Class3 Class3 Class3 Class3 Class2 Class2
Max Input Voltage 4.5V 4.5V 4.5V 4.5V 4.5V 5.5V 6V 6.3V
Package 209pin BGA 7x7mm2 169pin BGA 12x12mm2 139pin BGA 10x10mm2 139pin BGA 10x10mm2 120pin uBGA 6x6mm2 48pin QFN 6x6mm2 40pin QFN 5x5mm2 48pin QFN 6x6mm2
Ball Pitch 0.4mm 0.8mm 0.65mm 0.65mm 0.5mm 0.4mm 0.4mm 0.4mm
Targeted devices all AM37x, DM37x except for OPP1G, only TPS65950A3 for DM37x at OPP1G all AM37x, all DM37x all AM37x, DM37x except for OPP1G all AM37x, DM37x except for OPP1G Must use TPS65921B1 for DM37x OPP1G, otherwise any TPS65921 can be used all AM37x, DM37x all AM37x, DM37x all AM37x, DM37x

Thermal Use Cases

Power Information

SW Overview

Linux

Refer to the AM37x EVM Software Developer's Guide for instructions on setting up the software.

Instructions for building Qt - A cross-platform application and user interface (UI) framework.

Windows

Coming soon: a Windows® Embedded CE (WinCE) Board Support Package (BSP) and Software Development Kit (SDK) for AM/DM37x.

Peripheral Overview

Microprocessor Unit (MPU) Subsystem

The MPU subsystem integrates the following:

  • ARM® Cortex™-A8 core
  • ARM Version 7™ ISA: Standard ARM instruction set + Thumb®-2, Jazelle® RCT Java accelerator, and media extensions
  • NEON™ SIMD coprocessor (VFP lite + media streaming instructions)
  • Cache memories
    • Level 1: 32KB instruction and 32KB data—4-way set associative cache, 64 bytes/line
    • Level 2: L2 cache and cache controller are embedded within the ARM Cortex-A8 CPU - 256KB, 8 ways associative, 64 bytes/line, parity and error-correction code (ECC) supported
  • Memory management unit (MMU) and translation look-aside buffers (TLBs)
  • Interrupt controller (MPU INTC) of 96 synchronous interrupt lines
  • Debug, trace, and emulation features: ICE-Crusher, ETM, ETB modules.

For additional details on CortexA8 click here

IVA2.2 Subsystem - DM37x Only

The device includes the high-performance Texas Instruments image video and audio accelerator (IVA2.2), based on the TMS320DMC64X+ VLIW digital signal processor (DSP) core. The internal architecture is an assembly of the following components:

  • High-performance TI DSP (TMS320DMC64X+) integrated in a megamodule, including local L1/L2 cache and memory controllers
  • L1 RAM and L2 RAM and ROM
  • Video hardware accelerator module, including local sequencer
  • Dedicated enhanced data memory access (EDMA) engine to download/upload data from/to memories and peripherals external to the subchip
  • Dedicated memory management unit (MMU) for accessing level 3 (L3) interconnect address space
  • Local interconnect network
  • Dedicated modules SYSC and WUGEN in charge of power management, clock generation, and connection to the power, reset, and clock manager (PRCM) module

Camera Image Signal Processor

The camera ISP is a key component for imaging and video applications such as video preview, video record, and still-image capture with or without digital zooming.

The camera ISP provides the system interface and the processing capability to connect RAW image-sensor modules to the device.

The camera ISP implements 12 bit parallel inteface. Their purpose is to act as a physical connection between the outside pins for connecting external sensors and the internal receivers. By configuring the outside PHY's and feeding the receivers, the camera ISP supports up to two simultaneous pixel flows from external sensors. Only one of the data flow can use the Video processing hardware while the other must go to memory. it can support upto 150 MHz Pclk when operating in 8 bit mode and 75 MHz for 12 bit interface.

Display Interface Subsystem

The display interface subsystem provides the logic to display a video frame from the memory frame buffer (either SDRAM or SRAM) on a liquid-crystal display (LCD) panel or a TV set. The display subsystem integrates the following elements:

  • Display controller (DISPC) module
  • Remote frame buffer interface (RFBI) module
  • NTSC/PAL video encoder

The display controller and the DSI protocol engine are connected to the L3 and L4 interconnect; the RFBI and the TV out encoder modules are connected to the L4 interconnect.

2D/3D Graphics Accelerator (SGX) - AM3715 and DM3730 only

The 2D/3D graphics accelerator (SGX) subsystem accelerates 2-dimensional (2D) and 3-dimensional (3D) graphics applications. The SGX subsystem is based on the POWERVR® SGX core from Imagination Technologies. SGX is a new generation of programmable PowerVR graphic cores. Targeted applications include feature phones, PDA, and hand-held games.

The SGX graphics accelerator efficiently processes a number of various multimedia data types concurrently:

  • Pixel data
  • Vertex data
  • Video data
  • General-purpose processing

This is achieved using a multithreaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.

The SGX subsystem is connected by a 64-bit master and a 32-bit slave interface to the L3 interconnect.

Memory Subsystem

General-Purpose Memory Controller (GPMC)

The general-purpose memory controller (GPMC) is dedicated to interfacing external memory devices:

  • Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
  • Asynchronous, synchronous, and page mode (only available in non-muxed mode) burst NOR flash devices
  • NAND flash
  • Pseudo-SRAM devices
  • 1b, 4b, and 8b ECC Detection only. Please see the GPMC ECC article on how to use NAND Memories that require 4b and 8b ECC correction.

Tips for configuring GPMC registers can be found at the following wiki: Tips_for_configuring_OMAP35x,_AM35x,_and_AM-DM37x_GPMC_registers

SDRAM Controller Subsystem (SDRC)

The SDRC subsystem module provides connectivity between the device POP-ed SDRAM memory components. The module includes support for low-power double-data-rate SDRAM (LPDDR1).
CBP and CBC package only syupports PoP memory. CUS only supports discreate memory.The SDRC subsystem provides a high-performance interface to a variety of fast memory devices. It comprises two submodules:

  • The SDRAM Memory Scheduler (SMS), consisting of scheduler and virtual rotated frame-buffer (VRFB) modules
  • The SDRAM Controller (SDRC)

AM37x SDRC registers would allow you to compute register value to be programmed in the AM37x SDRC module depending on the mDDR memory that you are using.

On-Chip Memory (OCM) Subsystem

The on-chip memory subsystem consists of two separate on-chip memory controllers, one connected to an on-chip ROM (OCM_ROM) and the other connected to an on-chip RAM (OCM_RAM). Each memory controller has its own dedicated interface to the L3 interconnect.

System Direct Memory Access (SDMA)

The System Direct Memory Access (SDMA), also called DMA4, performs high-performance data transfers between memories and peripheral devices without microprocessor unit (MPU) or digital signal processor (DSP) support during transfer.


Interrupt Controller (INTC)

The device provides three interrupt controller (INTC) modules:

  • MPU subsystem INTC (INTCPS): This module handles all MPU-related events, using Priority Threshold. It communicates with the public ARM Cortex-A8 processor using a private local interconnect, and runs at half the speed of the processor.
  • IVA2.2 subsystem INTC: This module is a specific combination of WUGEN (wake-up generator) and the C64x+ DSP interrupt controller (IC).
  • Modem INTC: This module is an L4-mapped INTC that allows the regrouping of all the interrupts sent to the modem subsystem in stacked mode. It is seen as a level 2 INTC by the MPU and IVA2.2 subsystems. This modem INTC is integrated in the stand-alone device, but it is used only with the stacked modem.

Interprocessor Communication (IPC)

Communication between the on-chip processors of the device uses a queued mailbox-interrupt mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel between two processors through a set of registers and associated interrupt signals by sending and receiving messages (mailboxes).
The mailbox module includes these features:

  • Two mailbox message queues for microprocessor unit (MPU) and imaging video and audio accelerator (IVA2.2) communications.
  • Flexible assignment of receiver and sender for each mailbox through interrupt configuration
  • 32-bit message width
  • Four-message FIFO depth for each message queue
  • Message reception and queue-not-full notification using interrupts
  • Support of 16-/32-bit addressing scheme
  • Power management support
  • Automatic idle mode for power savings

Memory Management Units (MMU)

The device contains three memory management units (MMUs):

  • Microprocessor unit (MPU) MMU
  • Camera MMU
  • Image Video and Audio accelerator (IVA2.2) MMU

The camera MMU and IVA2.2 MMU share the same architecture.
The MMU instances include the following main features:

  • N entries fully associative translation look-aside buffer (TLB) with N = 8 for the camera MMU and N = 32 for the IVA2.2 MMU
  • 1 interrupt line out to the MPU subsystem
  • 32-bit virtual addresses, 32-bit physical address
  • Mapping size: 4KB and 64KB pages, 1MB section, and 16MB supersection
  • Predefined (static) or table-driven (hardware table walker) software translation strategies

Timers

The device includes several types of timers used by the system software, including 11 general-purpose timers (GP timers), 2 watchdog timers (WDTs), a 32-kHz synchronized timer.
The 2 WDTs are clocked with 32-kHz clocks. The 32-kHz synchronized timer, which is reset only at power up, provides the operating system with a stable timing source that stores the relative time since the last power cycle of the product. Finally, 11 GP timers, which are useful simply as basic timers, are included to generate time-stamp-based interrupts to the system software or to use as a source of pulse-width modulation (PWM) signals.

Multimaster High-Speed I2C Controller

The device contains four multimaster high-speed (HS) inter-integrated circuit (I2C)™ controllers (I2Ci, where i = 1, 2, 3, or 4), each of which provides an interface between a local host (LH), such as the microprocessor unit (MPU) subsystem, and any I2C-bus-compatible device that connects through the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each HS I2C controller can be configured to act like a slave or master I2C-compatible device. Moreover, each HS I2C controller can be configured in serial camera control bus (SCCB) mode (the SCCB is a serial bus developed by Omnivision Technologies, Inc.) to act as a master on a 2-wire SCCB bus. Only HS I2C2 and I2C3 can be configured in SCCB mode to act as a master device on a 3-wire SCCB bus.
The fourth HS I2C4 controller (I2C4) is in the power, reset, and clock management (PRCM) module to perform dynamic voltage control and power sequencing.

HDQ/1-Wire Module

The HDQ/1-Wire module implements the hardware protocol of the master functions of the Benchmark HDQ and the Dallas Semiconductor 1-Wire® protocols. These protocols use a single wire for communication between the master (HDQ/1-Wire controller) and the slaves (HDQ/1-Wire external compliant devices).

The HDQ and 1-Wire module has a generic L4 interface and is intended to be used in an interrupt-driven fashion. The one-pin interface is implemented as an open-drain output at the device level. The HDQ operates from a fixed 12-MHz functional clock provided by the PRCM module. Only the MPU subsystem uses the HDQ/1-Wire module.

The main features of the HDQ/1-Wire module support the following:

  • Benchmark HDQ protocol
  • Dallas Semiconductor 1-Wire® protocol
  • Power-down mode

The HDQ/1-Wire module provides a communication rate of 5K bits/s over an address space of 128 bytes.

A typical application of the HDQ/1-Wire module is the communication with battery monitor (gas gauge) integrated circuits.

UART/IrDA/CIR Overview

The device contains three universal asynchronous receiver/transmitter (UART) devices controlled by the microprocessor unit (MPU):

  • Three UART-only modules, UART1, UART2 and UART4 are pinned out for use as UART devices only. UART1 and UART2 must be programmed by setting the UARTi.MDR1_REG[2:0] MODE_SELECT field to one of the three UART operating modes.
  • UART3, which adds infrared communication support, is pinned out for use as a UART, infrared data association (IrDA), or consumer infrared (CIR) device, and can be programmed to any available operating mode.

Note: Due to availability of pins UART4 is not available on CUS package.

McSPI

The multichannel serial port interface (McSPI) is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. The McSPI modules differ as follows: SPI1 supports up to four peripherals, SPI2 and SPI3 support up to two peripherals, and SPI4 supports only one peripheral.

McBSP

The multi-channel buffered serial port (McBSP) provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips (digital base band), audio and voice codec, etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.

The device provides five instances of the McBSP module.

Universal Serial Bus (USB)

The device includes a high-speed universal serial bus (USB) OTG controller and a high-speed USB host subsystem.

Multimedia Card/Secure Digital/Secure Digital I/O (MMC/SD/SDIO) Card Interface

The processor contains three multimedia card high-speed/secure data/secure digital I/O (MMC/SD/SDIO) host controllers which provides an interface between a local host (LH) such as a microprocessor unit (MPU) or digital signal processor (DSP) and either MMC, SD memory cards, or SDIO cards and handles MMC/SD/SDIO transactions with minimal LH intervention.

The application interface manages transaction semantics. The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness.

The application interface can send every MMC/SD/SDIO command and either poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.

The application interface can read card responses or flag registers. It can also mask individual interrupt sources. All these operations can be performed by reading and writing control registers. The MMC/SD/SDIO host controller also supports two DMA channels.

Please check the SD-MMC_Usage_Notes_on_OMAP35x_and_AM37x wiki for more information on designing in MMC/SD devices with AM/DM37x.

General Purpose I/O (GPIO) Interface

The general-purpose interface combines six general-purpose input/output (GPIO) banks.

Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 192 (6 x 32) pins.

These pins can be configured for the following applications:

  • Data input (capture)/output (drive)
  • Keyboard interface with a debounce cell
  • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations.
  • Wake-up request generation in idle mode upon the detection of external events.

These modules do not include pad control (pull up/down control, open-drain feature).


Development and Reference Designs

EVM & Development Boards

  • EVM - AM37x EVM Schematic & board reference files are available here.
  • BeagleBoard xM available for Open Source design. community-supported platform that can be used as the basis for building more complete evelopment systems and as a target for community software baselines.
  • GEL files and configuration files for Code Composer Studio can be found here.
  • Embest DevKit8500D Evaluation board based on TI DM3730 processor supports for linux2.6.32, Android2.2 and WinCE6.0 operating systems. (DevKit8500A is also available for TI AM3715)
  • Embest SBC8530 uses POP (Package on Package) CPU/Memory chip to interface the 1GHz DM3730 processor to 512MBytes of Nand flash and 512MBytes of DDR SDRAM and features serial, 4 USB Host, USB OTG, Ethernet, WiFi/BT, Audio, TF, LCD, touch screen, DVI-D and S-Video interfaces on board, supporting for linux2.6.32, Android2.2 and WinCE6.0 operating systems.

Power Companion Reference Design

Design in Guide for TPS65023

Design in Guide for TPS65073


Related End Equipment

These links provide block diagrams and design considerations for various products.

Why AM/DM37x - FAQ's

  • Pin for Pin compatible set of devices for design flexibility
    • All AM/DM37x devices are all software and pin for pin compatible in same package type
    • All AM/DM37x devices are partial pin compatible with OMAP35x devices
    • Core software for all AM/DM37x devices is software compatible with AM35x and OMAP35x devices
  • How can I determine which product in AM/DM37x family is best choice
    • Please refere to the product matrix to see the different features supported by each device.
  • What are key care abouts for board design with AM/DM37x
  • Where can I get information on Wireless Connectivity?
    • Please refer to wiki to get more examples as well as hardware user guides.
  • Where can I get reflow profile for CBP / CBC / CUS packages
  • How can i determine AM37x would be able to meet my feature needs with existing pinmux.

Useful Links

AM37x/DM37x Schematic Checklist

DSP & ARM MPU Selection Tool

Sitara ARM Microprocessors Forum - Visit this site to ask questions and search for answers

Sitara Prodct line