AM18x To AM335x Hardware Migration Guide
- 1 Introduction
- 2 Software Migration Guide
- 3 Basic Feature comparison
- 4 Hardware Migration
- 4.1 CPU and Memory
- 4.2 External Memory Interfaces
- 4.3 Power, Reset, and Clock Management
- 4.4 Multimedia Hardware Components
- 4.5 Communication Interfaces
- 4.6 Timers
- 4.7 Misc
- 4.8 New Interfaces in AM335x
- 4.9 Pin and package
This article documents the differences between the TI AM18x ARM-9 based processor and the TI AM335x Cortex-A8 based processor. Note AM18x is the ARM-only version of this processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.
Software Migration Guide
For more information on software migration, please see:
Basic Feature comparison
The figures and table below show a comparison of the basic features of the AM18x and AM335x devices. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.
|Device Family||AM1808/6/2 - ARM 9|| AM3357/6/2 - CortexA8 |
AM3359/8/4 - CortexA8 with SGX 530
|Packages|| 361-ball PBGA (ZCE), .65-mm Ball Pitch
361-ball PBGA (ZWT), .80-mm Ball Pitch
| 284-pin nFBGA (ZCE), .65-mm Ball Pitch with VCA|
324-Pin nFBGA (ZCZ), .80-mm Ball Pitch Full Array
|Co-processors and Subsystems|
|ARM Processor|| ARM 9 up to 450 MHz;
16KB Instruction and Data Caches
|Cortex-A8 up to 1.0 GHz|
|Supported CVdd: 1.0/1.1/1.2/1.3 V||Supported OPP: 50/100/120/SRTurbo|
|Neon Co-processor||not present||Y|
|SGX530 3D Graphics Engine||not present||Y|
|Memory Subsystem|| mDDR/DDR2 Controller;
| EMIF; |
|Crypto hardware accelerators||not present||Y|
|USB||USB 1.1, USB 2.0||USB 2.0 [x2]|
|eMAC||10/100 Mbps||10/100/1000 Mbps|
|UART||3 (none with IrDA)||6 (all with IrDA)|
|GPIO||9 banks||4 banks|
|ADC/TS||not present||8ch 12bit|
|SATA Controller||Y||not present|
|Power, Reset, and Clock Management|
|ETM & ETB||Y||Y|
|IEEE 1500 support||not present||Y|
|GP Timer||3 64b or 6 x32b Timers||7|
CPU and Memory
AM18x is based on an ARM 9 processor, while AM335x is based on an ARM Cortex A8. The table below shows a comparison between these two devices.
|ARM Processor||ARM 9||ARM Cortex™ A8|
|OPP/CVdd Supported||1.0/1.1/1.2/1.3 V||50%/100%/120%/SRTurbo (.95/1.1/1.2/1.26 V)|
|Operating Frequencies||100/200/375/456 MHz (@1.0/1.1/1.2/1.3 V)||275/550/650/1000 MHz (@50%/100%/120%/SRTurbo)|
|L1 Instruction Cache||16 Kbytes||32 Kbytes|
|L1 Data Cache||16 Kbytes||32 Kbytes|
|L1 with SED||No||Yes|
|L2 Cache||N/A||256 Kbytes|
|L2 with ECC||N/A||Yes|
|ROM Size||64 Kbytes||176 Kbytes|
|RAM Size||8 Kbytes||64 Kbytes|
AM18x does not contain a co-processor.
The Neon co-processor is supported on AM335x.
AM18x does not contain a dedicated wake-up controller.
AM335x integrates an ARM Cortex M3 core that manages entry and exit of various stand-by and deep-sleep modes.
AM335x supports a SGX530 3D Graphics Engine, with maximum frequency of 200 MHz.
AM18x does not contain a graphics engine.
Programmable Real-Time Unit SubSystem (PRUSS)
The PRUSS supported on AM335x is an enhanced version of that on AM18x. In both devices, the PRUSS integrate two independent 32-bit Load/Store RISC processors, or Programmable Real-time Units (PRUs). The PRU cores run at half the CPU frequency on AM18x and at 200 MHz on AM335x.
Enhancements on AM335x include:
- Additional data memory (8 KB compared to 512 B) and instruction memory (8 KB compared to 4 KB) with SED
- 12 KB Shared RAM with SED
- Enhanced GPIO, adding serial, parallel, and MII capture of the PRU input/output pins
- Scratch pad shared by the PRU cores
- Multiplier with optional accumulation (MAC)
- Internal peripheral modules (UART, eCAP, MII_RT, MDIO, and IEP)
The constant table and PRUSS INTC system events are also updated on AM335x.
AM18x has 128KB RAM.
AM335x has 64KB RAM.
External Memory Interfaces
AM18x supports two controllers (EMIFA and DDR2/mDDR memory controller) for interfacing with external memories.
The EMIFA is used to interface with asynchronous and SDRAM external memories. Up to 5 CS signals are supported. The controller supports the following asynchronous devices:
- NOR Flash (8-/16-bit-wide data),
- NAND Flash (8-/16-bit-wide data) with 4-bit ECC,
- 16-bit SDRAM with 128 MB address space
The DDR2/mDDR memory controller is used to interface with DDR2 SDRAM devices and mobile DDR (mDDR) SDRAM devices. (Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported.) The controller supports a 16-bit wide data path and one CS signal. Only little endian mode is supported. The following CAS latencies and internal banks are supported:
- CAS latencies:
- DDR2: 2, 3, 4, and 5
- mDDR: 2 and 3
- Internal banks:
- DDR2: 1, 2, 4, and 8
- mDDR: 1, 2, and 4
AM335x supports a memory subsystem that includes the GPMC and EMIF for interfacing with external memories.
The GPMC provides an 8/16-bit asynchronous interface for:
- Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
- Asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash devices
- NAND Flash
- Pseudo-SRAM devices
The controller supports up to 7 CS signals and uses Hamming code to support 1-bit ECC and an integrated Error Locator Module (ELM) to support 4-bit, 8-bit, or 16-bit ECC based on BCH algorithms.
The EMIF provides a 16-bit interface to mDDR (LPDDR1), DDR2, and DDR3 memories. The controller supports a 16-bit wide data path and one CS signal. Both big and little endian modes are supported. The following CAS latencies and internal banks are supported:
- CAS latencies:
- DDR2 => 3, 4, 5, 6, and 7
- DDR3 => 5, 6, 7, 8, 9, 10, and 11
- mDDR => 2, 3, and 4
- Internal banks:
- DDR2 => 1, 2, 4, and 8
- DDR3 => 1, 2, 4, and 8
- mDDR => 1, 2, and 4
Power, Reset, and Clock Management
The following table compares the power supplies for AM18x and AM335x:
|CVDD||Core Logic Supply Voltage (variable)||1.3/ 1.2/ 1.1/ 1.0 V|
|RVDD||Internal RAM Supply Voltage||1.2-1.32V|
|RTC_CVDD||RTC Core Logic Supply Voltage||1.2-1.32V|
|PLL0_VDDA||PLL0 Supply Voltage||1.2-1.32V|
|PLL1_VDDA||PLL1 Supply Voltage||1.2-1.32V|
|SATA_VDD||SATA Core Logic Supply Voltage||1.2-1.32V|
|USB_CVDD||USB0, USB1 Core Logic Supply Voltage||1.2-1.32V|
|USB0_VDDA18||USB0 PHY Supply Voltage||1.8-1.89V|
|USB0_VDDA33||USB0 PHY Supply Voltage||3.3-3.45V|
|USB1_VDDA18||USB1 PHY Supply Voltage||1.8-1.89V|
|USB1_VDDA33||USB1 PHY Supply Voltage||3.3-3.45V|
|SATA_VDDR||SATA PHY Internal Regulator Supply Voltage||1.8-1.89V|
|DDR_DVDD18||DDR2 PHY Supply Voltage||1.8-1.89V|
|DDR_VREF||DDR2/mDDR reference voltage||0.49*DDR_DVDD18-0.51*DDR_DVDD18|
|DDR_ZP||DDR2/mDDR impedance control, connected via 50Ω resistor to Vss||Vss|
|DVDD3318_A||Power Group A Dual-voltage IO Supply Voltage||1.8/3.3 - 1.89/3.45V|
|DVDD3318_B||Power Group B Dual-voltage IO Supply Voltage||1.8/3.3 - 1.89/3.45V|
|DVDD3318_C||Power Group C Dual-voltage IO Supply Voltage||1.8/3.3 - 1.89/3.45V|
|VDD_MPU *||MPU domain||0.95V - 1.26V|
|CAP_VDD_RTC||RTC domain input/LDO output||1.1V|
|VDDS_DDR||DDR IO domain (DDR2 / DDR3)||1.8V / 1.5V|
|VDDS||Dual voltage IO domains||1.8V|
|VDDS_SRAM_CORE_BG||Core SRAM LDOs, Analog||1.8V|
|VDDS_SRAM_MPU_BB||MPU SRAM LDOs, Analog||1.8V|
|VDDS_PLL_DDR||DPLL DDR, Analog||1.8V|
|VDDS_PLL_CORE_LCD||DPLL Core and LCD, Analog||1.8V|
|VDDS_PLL_MPU||DPLL MPU, Analog||1.8V|
|VDDS_OSC||System oscillator IOs, Analog||1.8V|
|VDDA1P8V_USB0||USB PHY, Analog, 1.8V||1.8V|
|VDDA1P8V_USB1||USB PHY, Analog, 1.8V||1.8V|
|VDDA3P3V_USB0||USB PHY, Analog, 3.3V||3.3V|
|VDDA3P3V_USB1||USB PHY, Analog, 3.3V||3.3V|
|VDDSHV1||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV2 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV3 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV4||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV5||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV6||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV1||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV2 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV3 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV4||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV5||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV6||Dual Voltage IO domain (3.3-V operation)||3.3V|
|DDR_VREF||DDR SSTL/HSTL reference input (DDR2/DDR3)||0.50*VDDS_DDR|
|USB0_VBUS||USB VBUS comparator input|
|USB1_VBUS||USB VBUS comparator input|
|USB0_ID||USB ID input||1.8V|
|USB1_ID||USB ID input||1.8V|
* Note: These voltage rails are not available in the 13x13 package.
The following table compares the power modes for AM18x and AM335x:
|Power Mode||Device Power Excluding IO (mW)||Description|
|RTC-Only||0.02||Only RTC voltage rail is powered; core and I/O rails are powered off.|
|DeepSleep||10.93||The 24MHz CLKIN is cut off and voltage is applied to the various core and I/O rails.|
|Standby||36.13||PLL0 is powered down/disabled and the system is operating in bypass mode with the 24MHz CLKIN as the system clock. The ARM is in the wait for interrupt sleep mode and all peripherals are disabled.|
|Typical/Active*|| 267.93 - 1.2V/300MHz
376.82 - 1.3V/456MHz
|The device power values for typical/active mode assume the ARM is running at typical activity and mDDR, EDMA3CC, EDMA3TC0, EDMA3TC1, McASP0, SPI0, and GPIO are enabled and all other modules are not used and disabled.|
* Note, the Power and Sleep Controller (PSC) is used to enable and disable any peripheral. This prevents consumption of any unnecessary power.
|Power Mode||Total Device Power (mW)||Description|
|RTC-Only||0.08||Only RTC voltage domain is alive. Optionally, SDRAM can be kept in self-refresh which will reduce the boot time.|
|DeepSleep0||5||PD_PER peripheral & CortexA8 / MPU register information will be lost. On-chip peripheral register (context) information of PD_PER domain needs to be saved by application to SDRAM before entering this mode. SDRAM is in self-refresh. For wakeup, boot ROM executes and branches to peripheral context restore followed by system resume.|
|DeepSleep1||9||On-chip peripheral registers are preserved. CortexA8 context/registers are lost and hence application needs to save them to MPU Subsystem or L3 OCMC RAM or SDRAM before entering DeepSleep. SDRAM is in self-refresh. For wakeup, boot ROM executes and branch to system resume.|
|DeepSleep2||13||Everything is preserved including SDRAM.|
|Standby||22||Everything is preserved including SDRAM. DS2 + OSC ON.|
|Active||< 1000||All Features.|
The following table compares the clock inputs for AM18x and AM335x:
|Ref clk for PLL||Divide down of PER PLL output (PLL uses Master Osc)||12 - 50 MHz|
|Ref clk for RTC||External 32.768-kHz crystal or external clock source of the same frequency||32768 Hz Precise|
|CLK_M_OSC||Master Oscillator||19.2, 24, 25, 26 MHz|
|CLK_32KHZ||Divide down of PER PLL output (PLL uses Master Osc)||32768 Hz Precise|
|CLK_RC_32KHZ||Internal RC Oscillator||16 - 60 kHz|
|CLK_32K_RTC||External 32768 Hz crystal with internal 32K Osc or external 32768 Hz clock||32768 Hz Precise|
On AM18x, the reference clock for the PLL has the option to be sourced from the on-chip oscillator or an external clock on the OSCIN pin. The AM335x has the option to obtain the 32KHz clock from the high frequency 20MHz clock using an internal RTCDIVDER. If this is used, an external 32KHz clock source is not necessary. The 32KHz provides a clock for the following modules:
AM18x has the following phase-locked loop controllers (PLLCs), driven by the reference clock for PLLs:
- PLL0 - for ARM RAM/ROM, Shared RAM, UART0, EDMA, SPI0, MMC/SDs, VPIF, LCDC, SATA, uPP, DDR2/mDDR bus ports, USB2.0, HPI, PRU, EMIFA, SYSCFG, GPIO, PLLCs, PSCs, I2C1, EMAC/MDIO, USB1.1, ARM INTC, ARM, EMAC RMII clock, I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP serial clock, Observation clock
- PLL1 - for mDDR/DDR2 PHY
AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):
- Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRUSS IEP, Debugss
- Peripheral (Per) PLL - for USB PHY, PRUSS UART, MMC/SD, SPI, I2C, UART
- MPU PLL - for MPU Subsystem (includes Cortex A-8)
- Display PLL - for LCD Pixel Clock
- DDR PLL - for EMIF
Power Management Feature Comparison
|HW Provisions for Power Optimization/ Control||AM18x||AM335x|
| Individually Switchable Power Domains
|| Not supported
|| Full support for Individual Power Domain ON/OFF:
VDD_MPU, VDD_CORE, VDD_PER, VDD_SGX and SRAMs. In RTC_Only mode, even WAKEUP Domain can be OFF'd.
| Dynamically gating OFF of Clocks to one/more of groups of
modules (clock domains) when inactive to conserve power
| Operating Voltage-Frequencies (OPPs)
|| 1.0/1.1/1.2/1.3 V
| OPP50, OPP100, OPP120, SRTurbo |
| Adaptive Voltage Scaling
|| Not supported
||Class 2B Smart Reflex|
| SRAM memory retention
| Logic (Register) State Retention
|| Not Supported
|| Not Supported|
| Low Power Deep-Sleep State w/ Auto Wakeup
|| GPIO0 bank, UART0, RTC, I2C0, DMTimer 1ms, USB Resume and TSC/ ADC Control events |
| RTC Only Cold State
| Splitting Of Primary Voltage Supply Rails
RTC has own voltage domain
|VDD_CORE, VDD_MPU*, VDD_RTC|
- * On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.
The available bootmodes for AM18x and AM335x are shown in the table below.
|Y||Y||NOR|| This mode allows booting over the asynchronous interface. ARM pulls data from a memory device such as a NOR flash. |
For AM18x, NOR Flash should be connected to the EMIFA peripheral on EMA_CS.
For AM335x, NOR Flash should be connected to the GPMC peripheral on GPMC_CSN0.
|Y||Y||NAND|| This mode starts downloading code from an NAND memory. |
For AM18x, NAND flash should be connected to the EMIFA peripheral on EMA_CS. The ALE and CLE pins of the NAND device should be connected to the EMA_A and EMA_A pins of the EMIFA peripheral, respectively.
For AM335x, NAND flash should be be connected to the GPMC peripheral on GPMC_CSN0. The ALE and CLE pins of the NAND device should be connected to GPMC_ADVN_ALE and GPMC_BEN0_CLE, respectively.
|Y||Y||SPI|| This mode starts downloading code from an SPI EEPROM or SPI Flash. |
For AM18x, the external SPI device should be connected to the SPI chip select 0 signal (SPI0_SCS or SPI1_SCS). SPI EEPROM devices must use 16-bit addressing, and its read command must equal 0x03.
For AM335x, the external SPI device should be connected to the SPI0 chip select 0 signal (SPI0_CS0). SPI EEPROM devices must use 24-bit addressing, and its read command must equal 0x03.
|Y||Y||UART|| In this mode, the UART sends a BOOTME request to the UART peripheral and waits for a response along with code from a host processor.|
Both AM18x and AM335x must be booted using a baud rate of 115200.
|N||Y||MMCSD|| This mode starts booting code from an MMC/SD Controller. |
For AM335x, the MMC/SD cards should connected to either MMC0 or MMC1.
|N||Y||EMAC|| This mode starts booting code from the EMAC port. |
For AM335x, EMAC boot uses the CPGMAC port 1 of the device.
|Y||N||HPI|| This mode allows for booting code through the HPI port. |
For AM18x, HPI boot happens from the HPI0 peripheral in 16-bit mode.
|Y||N||I2C|| This mode starts downloading code from an I2C. |
For AM18x, either I2C0 or I2C1 can be used.
Multimedia Hardware Components
The AM335x LCD controller is an upgraded version from the controller in AM18x. The enhancements include:
- Higher resolution support (up to WXGA) vs XGA on AM18x
- 24bit output (8bpp) vs 16bit output on AM18x
- Increased horizontal blanking fields HSW/HFP/HBP to 10 bits vs 8bits on AM18x
The VPIF module does not exist on AM335x.
The AM18x and AM335x devices support different versions of industry standards (shown below). The FIFO sizes are also different on each device: AM335x supports a 1024-byte FIFO, and AM18x only supports a 512-bit FIFO.
|Spec Compliance|| MMC v4.0
SD Physical Layer v1.1
| MMC v4.3|
SD Physical Layer v3.0
|Data Width *||8-bit (MMC0/1)||8-bit (MMC0/1/2)|
|Max Clock Rate|| 20MHz (MCC),
| 48MHz (MCC),|
* Note the supported data width is subject to pinmux constraints.
AM18x supports one USB 1.1 OHCI (Host) With Integrated PHY (USB1) and one USB 2.0 OTG Port With Integrated PHY (USB0). The USB 2.0 OTG peripheral supports 4KB endpoint FIFO RAM.
AM335x supports two USB 2.0 High Speed OTG Ports with integrated PHY. This USB peripheral supports 32KB endpoint FIFO RAM.
Both AM18x and AM335x support 3 I2C ports.
The AM18x I2C generates 7 interrupts to the CPU and contains a I2C data transmit register (ICDXR) and I2C receive shift register (ICRSR) each holding up to 8 data bits.
The AM335x I2C generates 12 interrupts to the CPU. The I2C's built-in configurable FIFOs (32 bytes size) are used for buffered read or write.
AM18x has 3 UART ports, all supporting modem control signals. None of the UART ports support IrDA. The AM18x UARTs are functionality compatible with the TL16C550 UART. AM18x UARTs support 16-byte transmit and receive FIFOs.
AM335x has 6 UART ports, all supporting IrDA / flow control and only 1 instance supporting full modem control. AM335x allows 1 instance of UART rx/ tx lines to be muxed with USB DP/ DM lines. The UARTs are functionality compatible with the TL16C750 (and TL16C550) UART. AM335x UARTs support 64-byte transmit and receive FIFOs.
The McASP ports on AM335x and AM18x are functionally identical. Note the McASP is a superset of the McBSP. It is suggested to use the McASP ports for McBSP functionality.
AM18x has 2 McBSP ports and 1 McASP ports. McASP0 supports up to 16 McASP serializers.
AM335x has no McBSP ports and 2 McASP ports. McASP0/1 support up to 4 McASP serializers.
Both AM18x and AM335x support two (2) SPI ports. The AM18x SPI supports 6 CS and 2-16 bit word length. The AM335x SPI supports 2 CS and 4-32 bit word length.
AM18x supports one Ethernet MAC with a maximum data rate of 100 Mbps. The AM18x MAC interfaces include MII/RMII and MDIO.
AM335x supports two Gigabit Ethernet MACs with an integrated switch, with reset isolation, and supporting 1588 precision time stamping. The AM335x MAC interfaces include MII/RMII/RGMII and MDIO.
eCAP/ eHRPWM/ eQEP
The eCAP and eHRPWM modules supported on AM18x and AM335x are identical. The eQEP module is a new interface on AM335x.
AM18x supports the eCAP and eHRPWM peripherals as separate modules. AM335x integrates eCAP, eHRPWM, and eQEP into a single subsystem.
The HPI module does not exist on AM335x. It is suggested to use GPMC to achieve 16-bit parallel port functionality.
The uPP module does not exist on AM335x.
The SATA controller does not exist on AM335x.
AM18x supports three (3) one 64-bit or two 32-bit GPTimers. All GPTimers are pinned out.
AM335x supports seven (7) 32-bit GPTimers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 4 GPTimers (DMTIMER4 - DMTIMER7) are pinned out.
AM18x supports 1 WDTimer that can be configured as one 64-bit or two 32-bit WDTimers.
AM335x supports 1 32-bit WDTimer.
AM18x and AM335x both support 1 RTC.
The AM335x RTC adds a keep alive LDO to power the RTC core logic and supports wake up events to the Cortex M3 for wake up.
AM18x supports 9 banks of GPIO signals. Each bank supports 16 GPIOs and one interrupt.
AM335x supports 4 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts.
New Interfaces in AM335x
The following are new interfaces in the AM335x device that do not exist in AM18x. Any details about these interfaces can be found in the Technical Reference Manual for AM335x.
- CAN - Controller Area Network Interface
Pin and package
The AM18x and the AM335x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM18x and the AM335x devices.
|Device||Size (mm)||Pitch (mm)||No. of Pins||Package Designator|
|AM18x||13 x 13 mm||0.65 mm||361||ZCE|
|16 x 16 mm||0.80 mm||361||ZWT|
|AM335x||13 x 13 mm||0.65 mm||298||ZCE|
|15 x 15 mm||0.80 mm||324||ZCZ|