AM335x Hardware Design Guide

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== Hardware Design Timeline → ==

Constructing the Block Diagram Selecting the Boot Mode Confirming Pin Multiplexing Compatibility Confirming Electrical and Timing Compatibility Designing the Power Subsystem Designing the Clocking Subsystem Floorplanning the PCB Creating the Schematics Laying out the PCB Testing / Debugging



Welcome to the Hardware Design Guide. The purpose of this guide is to walk hardware designers through the various stages of designing a board on this platform. The guide follows the structure shown in the Hardware Design Timeline above. Each design stage in the Timeline links to a collection of useful documentation, application notes, and design recommendations pertaining to that stage. Using this Guide, hardware designers can efficiently locate the resources they need at every step in the board design flow.

Constructing the Block Diagram

The first step in designing the hardware platform is to create a detailed block diagram.  The block diagram should contain all major system ICs and illustrate which I/O ports are used for device interconnection.  Below is a collection of resources to aid in the Block Diagram creation process.

  • The TMDXEVM3358 EVM is always a good source from which to start building a reference design for these devices. The technical documentation for the EVM is available.
  • The links at the TI website below provide block diagrams, application notes, tools, software, design considerations, and other related information for various products under category "Related End Equipments".
  • Select from a list of complementary devices to attach to AM335x device in your system:
    • Power Management Devices refer link

Selecting the Boot Mode

The block diagram should also indicate which interface will be used for booting this device.

  • These devices contain an on-chip ROM Bootloader:
    • The boot config pins are sampled at power-on-reset
    • Sets up system for boot depending on boot configuration selected
    • Depending on boot mode, copies image to internal RAM and then executes it
    • Maximum size of the boot image is 128KBytes
  • The following boot modes are supported:
    • NOR Flash boot
    • NAND Flash boot
    • SPI boot
    • SD/MMC boot
    • EMAC boot
    • UART boot
    • USB boot (like an ethernet card, not as mass storage)
  • If the first boot source fails to boot, the ROM will move on to the next one in the sequence. Keep in mind that some boot sources take some time to timeout if that boot source isn't available.
  • Read AM335x Technical Reference Manual Initialization Chapter to understand details on different boot modes
  • Key Boot Considerations:
    • It is recommended to include population options for other boot modes to aid in development
    • Boot pins have other functions after reset. Make sure your board design takes this into account when choosing pullup/down resistors for the boot pins.

Confirming Pin Multiplexing Compatibility

The AM335x device contains many peripheral interfaces. In order to reduce package costs while maintaining maximum functionality, many Approximately half of the AM335x terminals can multiplex up to eight signal functions. Although there are many combinations of pin-multiplexing that are possible, only a certain number of sets , called IO sets, are valid due to timing limitations. These valid IO sets were carefully chosen to provide many possible application scenarios for the user.

Texas Instruments has developed a Windows application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x based product design. This tool provides a way to select valid IO Sets of specific peripheral interfaces to insure the pin-multiplexing configuration selected for a design only uses valid IO Sets supported by AM335x.

Confirming Electrical and Timing Compatibility

A key step in the hardware design before beginning schematic capture is to confirm both DC and AC electrical compatibility between this device and the other ICs connected to it.

  • The device datasheet has important information with regards to timing and electrical characteristics.
  • For High Speed Interfaces you can run IBIS simulations using IBIS models provided for AM335x ZCE and ZCZ package to confirm signal Integrity.
  • Note: TI provides PCB layout specifications for the following interfaces, eliminating the need to perform electrical analysis:
    • lpDDR/DDR2/DDR3

Designing the Power Subsystem

Once the block diagram has been validated for pin multiplexing, electrical, and timing compatibility, the power sub-system can be designed. See the below resources on estimating power consumption and designing a matching power subsystem.

  • AM335x Power Consumption Summary: The AM335x Power Numbers discusses the power consumption for common system application usage scenarios for the AM335x ARM® Cortex™-A8 Microprocessors (MPUs). Power consumption is highly dependent on the individual user’s application; however, this document focuses on providing several AM335x application-usage case scenarios and the environment settings that were used to perform such power measurements.
  • AM335x Power Estimation Tool: The Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select Sitara processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce overall power consumption.
  • AM335x Power Solution

AM335x PMIC table.PNG

Designing the Clocking Subsystem

In addition to the power subsystem, the clocking subsystem needs to be designed to provide appropriate clocks to all ICs in the system. These clocks can be created by pairing crystals with internal oscillators within the system ICs, or they can be created by a separate clock generator. See the below information on designing the clocking subsystem for your design.

  • Key Considerations:
    • The device operation requires a 32k optional crystal and HF crystal with either 19.2,24,25,26 MHz reference clock for operation.
    • A 32.768-kHz clock input is an optional for the RTC.
    • For more details, please refer to the Clocking sections of the device datasheet and TRM.

Floorplanning the PCB

Before beginning schematic capture, it is recommended to floorplan the system PCB to determine the interconnect distances between the various system ICs.

Creating the Schematics

At this point in the design, it is time to start capturing the schematics. See the below collection of information to aid you in creating the schematics.

  • Key Considerations:
    • SDRAM (and other) output clocks are internally looped back
    • Don’t forget to install a JTAG connection
    • JTAG: Make sure to use the RTCK pin
  • It is often helpful to refer to example schematics throughout the schematic capture process: [TBD]
  • Make sure to use the canned schematics in the datasheet for the following interfaces:
    • lpDDR/DDR2/3
  • For detailed information on USB board design, see the USB 2.0 Board Design and Layout Guidelines application report SPRAAR7
  • During and after schematic capture, check your design against the schematic checklist:
  • Plan to have an internal schematic review to go through the schematic checklist and inspect other key areas of the schematic to look for inaccuracies, missing net connections, etc.

Below are Symbols, Footprints, and Simulation Models to aid in the design of the device placement and interconnects:

  • OrCad Symbols
  • Altium Symbols
  • Allegro footprints
  • Pin Names and Numbers
    • AM335x: Available in Data Sheet in [1]
  • BSDL Simulation Model

  • IBIS Simulation Models:

Laying out the PCB

After completing schematic capture, see the below information on laying out the PCB:

  • It is often helpful to refer to an example layout when designing a custom PCB: [TBD EVM Layout]
  • Make sure to follow the Layout Specifications for the following Critical Interfaces:
    • DDR2 - See Datasheet
    • mDDR/DDR3 - See Datasheet
  • Plan to have an internal PCB layout review with your design team to verify that net connection traces and the power distribution network were created correctly.

Board Bringup/Diagnostic

Once your custom PCB has been produced and assembled, refer to the below information on bringing-up and debugging the system.