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AM335x Schematic Checklist

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This article applies to the following devices:

Here are some links to some TI hardware designs based on AM335x:

If migrating from a previous TI processor, you can use the following migration guides as a start:

Don't forget to check the AM335x errata when designing a board (see the product folder on This will have important information on silicon issues which may alter your board design.

Other useful links:

Recommendations Specific to AM335x

Unused Signals

Signals on interfaces that are unused can typically be left as no connect. Many of the IOs have a Pad Control Register (see Chapter 9 of the TRM for more details) which gives control over the input capabilities of the I/O (RXACTIVE field in each conf_<module>_<pin> register). Software should disable the I/Os which are no connects (ie, RXACTIVE=0) as soon as possible in initialization. This RXACTIVE field defaults to "input active" for most signals, which means there is a potential for some leakage during powerup of the chip if the input floats to a mid-supply level before the software can initialize the I/O. This should only be a concern if you are attempting to power up the design with a minimum power consumption. Most designs should be able to tolerate this small amount of leakage in each floating I/O until the software has a change to disable it. After disabling the I/O, no leakage will occur.

Unused Power Rails

If ADC is not used...
  • Connect all TSC_ADC terminals (VREFP, VREFN, AIN[7:0], VDDA_ADC, and VSSA_ADC) to same ground as all VSS terminals.
If USB0 or USB1 is not used...
  • Connect the respective VDDA1P8V_USB terminal to any 1.8-V power supply and respective VDDA3P3V_USB terminal to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
    • The OTG_PWRDN and CM_PWRDN bits in the respective USB_CTRL register can be used to power down the unused USB PHY to minimize power supply leakage current. These bits default to the powered-up state after the AM335x device has been reset. The USB PHY can be powered down by setting both of these bits to "1".
  • The respective VBUS, ID, DP, and DM terminals may be connected to ground or left floating.
  • The respective CE terminal should be left floating.
If RTC internal oscillator is not used...
  • This can be the case when:
    • A 1.8 volt LVCMOS clock source is used rather than a crystal circuit
      • Connect the clock source to the RTC_XTALIN terminal, leave the RTC_XTALOUT terminal open-circuit, and connect VSS_RTC to VSS if using the ZCZ package option
    • The AM335x RTC is not used
      • Leave the RTC_XTALIN and RTC_XTALOUT terminals open-circuit, and connect VSS_RTC to VSS if using the ZCZ package option

System Issues


All pinmux settings must be verified using the TI Pinmux Tool to ensure valid IOSets have been used. The tool can be downloaded from


  • ensure all pullups connected to AM335x are pulled up to the correct I/O voltage to avoid any leakage between the I/O rails of AM335x. Each terminal has an associated voltage used to power its I/O cell. This can be found in the AM335x datasheet, in the Ball Characteristics table under the "ZCE Power/ ZCZ Power" column.
    • For example, if you want to pull up terminal SPI0_CS0 in any mux mode (gpio0_5, i2c1_scl, etc.), pull up the signal to VDDSHV6.

General Debug

  • output clocks CLKOUT1 and CLKOUT2 are present on terminals XDMA_EVENT_INTR0 and XDMA_EVENT_INTR1. If these are not used in your design, it is good to have test points on these signals to be able to monitor internal clocks.

Warm Reset

  • be sure to check the TRM for uses for warm reset. The warm reset signal should be used as an input (for example, connected to a push button) or output (to reset external devices during a POR). It cannot be used for both because of an errata with the clocking of the debounce circuitry.

Peripheral Clocking

Several peripheral clocks are required to have RXACTIVE bit set as input because they are used to retime read data returning to the device. We also recommend a series resistor located as close to the device as possible to reduce reflections on the clock. For the following peripherals, the associated signals should have a series resistor (33ohm) in line as close to the processor as possible when used in master mode (ie, AM335x drives the clock)
McASP (all clocks and frame syncs)

Low Power considerations

If you are designing for low power, here are some tips to help you optimize your design for low power

  • The TPS65217C and TPS65217D do not support RTC-only mode. TPS65218 does.
  • On early prototype boards, it is recommended to include small shunt resistors in the voltage rail paths of each of the following rails of AM335x: VDD_MPU, VDD_CORE, VDDS, VDDSHV1-6, VDDS_DDR. This will help you measure the power consumption of each rail and potential pinpoint high power consumption during development. You may also want to add these shunt resistors for other devices power supplies to be able to measure power for key devices. The AM335x EVMs have examples of these shunt resistors.
  • For production, these shunt resistors should be removed from the design (i.e. turned into a continuous plane), especially for designs using Smart Reflex.
  • Only GPIO0 signals are capable of wakeup signaling (to wakeup from DeepSleep or RTC modes). Connect wakeup sources only to these GPIOs (GPIO0_0 to GPIO0_31).
  • For your main clock (e.g. 24 MHz, etc.) you can use either a crystal or a LVCMOS square wave clock. There is a power benefit to using a crystal because there is hardware inside the chip that can shutoff the crystal entirely during DeepSleep0 (DS0). When using a square wave clock there is unfortunately no mechanism for automatically turning the clock off and on, which results in additional current consumption.
  • If your design uses VTT you should use a pin from GPIO bank 0 to control the regulator. This will enable the regulator to be switched off during DS0.
  • The Cortex M3 uses I2C0 for communication with the Power Management IC (PMIC) for purposes of reducing the voltage during DS0.


  • If you do not need RTC-only mode and the RTC timer feature, you do not need to include a 32KHz crystal. The 32KHz reference can come from the high frequency clock. Leave the RTC_XTALIN/RTC_XTALOUT pins as NC.
  • Per Advisory 1.0.30, VSS_OSC and VSS_RTC should be connected to system ground.
  • It is preferable to always have bias and dampening resistors that can help tune the crystal later. See section 4.2.2 of the datasheet for more details.

General DDR guidelines

These guidelines are applicable for all DDR designs:

  • It is very important to follow the DDR routing guidelines for your DDR type in the AM335x datasheet. These guidelines are very important to ensure a proper DDR design.
  • Ensure resistor for DDR_VTP is a high precision resistor as specified in the datasheet. A 49.9ohm 1% resistor is less expensive than a 50ohm 2% resistor and can be used for the DDR_VTP pin for cost sensitive designs.
  • When using a resistor divider for DDR_VREF, ensure resistors are high precision resistors as specified in the datasheet
  • allow for adequate decoupling capacitors on the DDR power rails both at the AM335x as well as the DDR SDRAM device(s)


  • DDR_VREF can be derived using a resistor divider with decoupling to both DDR supply and ground. Follow the recommendations as documented in the DDR2 Routing Guidelines of the data sheet.


  • For point-to-point DDR3 topologies (e.g. single x16 DDR3 IC), VTT termination is not needed. Designs using two x8 DDR3 IC’s may wish to consider using a termination regulator such as the TPS51200 for the address/control signals.
  • If using VTT termination...
    • Do not use VTT termination for DDR_RESET. It should be connected directly from the AM335x to DDR.
    • If VTT regulator is disabled during low power modes (e.g. by programming EN=0 using the TPS51200), DDR_CKE should not be connected to termination resistors. The active discharge capability of the regulator can cause a brief dip on this signal which can be problematic. This would likely be true of any VTT regulator with active discharge capability.
    • Termination for clock signals is VDDS_DDR (along with an AC coupling capacitor), whereas all other signals need to use VTT for the termination voltage. Check the datasheet for details.
  • If not using VTT termination, VREF should be obtained using a resistor divider (10Kohm 1%) with capacitive decoupling to ground, and should be used as a reference for both CA and DQ pins on the memory, as well as the VREF signal on AM335x. Be sure to use high precision (1%) resistors as specified in the datasheet. When not using VTT, be especially sure to follow the routing guidelines in the datasheet.


  • include a 22ohm series resistor on MMCx_CLK (as close to the processor as possible). This signal is used as an input on read transactions and the resistor will eliminate possible signal reflections on the signal which can cause false clock transitions.
    • this also requires you to set RXACTIVE=1 in the pinmux configuration for the MMC_CLK signal.
  • When connecting a device (card or eMMC), include 10k pullups on RST#, CMD, and all DAT signals.


  • pullups on both I2C signals (I2C_DATA and I2C_CLK) should be 4.7K. Ensure the pullups connect to the correct I/O voltage rail. See note on Pullups above.
  • if you are planning to use TI's software (SDK or Starterware), be sure to connect I2C0 to the PMIC, as this is the port used for PMIC control.


  • Please be sure to consult the silicon errata for the proper pinout of the LCD interface. There is a usage note titled, "LCD: Color Assignments of LCD_DATA Terminals".
  • Note that the EVM "fixes" the pin mapping through a CPLD on the daughterboard, so be extra careful to get the proper mapping!
  • A good example of a 24-bit hookup comes from the Starter Kit:
  • A good example of a 16-bit hookup comes from the BeagleBone Black. In this case they were preserving the other LCD pins for use by capes:
  • Notice that Red and Blue swap positions depending on whether you're outputting in 16-bit mode vs 24-bit mode (i.e. that's the errata...).


AM335x PMIC table.PNG

  • Check the product pages on each device for application notes specific for connecting the PMIC to AM335x. Also check the product data sheet for specific part numbers to be used for the AM335x
  • ensure current capabilities of DCDC switchers and LDOs meet the maximum demand of all devices that are attached. You can find the maximum current draw of all AM335x I/O rails in the datasheet. If these rails from the PMIC also power other devices, the maximum current draw of these devices need to be taken into consideration as well.
  • ensure I2C0 is used for communication to PMIC. All TI software distributions (linux SDK, Starterware, etc.) assumes the use of this interface with the PMIC.


  • recommend adding 0ohm resistor to VDDA_ADC in case you need to add a filter for noise on the ADC.
  • Check out the sampling voltage must not exceed the voltage of reference. Otherwise, it will affect the whole TSC_ADC system. (Ex: if you add pull up to 3.0V at the last four channel, this will lead to the abnormal work of the whole system, including the first four).


  • The AM335x USB0_ID and USB1_ID terminals should never be connected to any external voltage source. These terminals should be open-circuit when the respective USB port is configured to operate in USB peripheral mode, or should be connected to ground when the respective USB port is configured to operate in USB host mode.
  • USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points.
  • Typical connections for a USB peripheral:
    • USBx_DP and USBx_DM are connected directly to the USB connector
    • USBx_CE can be used if supporting charging. This generally would be connected to the enable of a charging source for the battery.
    • USBx_ID can be left unconnected
    • USBx_DRVVBUS is not used and can be left unconnected
    • USBx_VBUS should be connected directly to the VBUS pin on the USB connector
  • Typical connections for a USB host:
    • USBx_DP and USBx_DM are connected directly to the USB connector
    • USBx_CE is typically not used and can be left unconnected
    • USDx_ID should be grounded
    • USBx_DRVVBUS should be connected to the enable of the 5V VBUS power source.
    • USBx_VBUS should be connected to the output of the 5V VBUS power source
  • Typical connections for a USB host with USB hub:
    • USBx_DP and USBx_DM are connected directly to the USB hub upstream port. The hub then distributes these signals to the downstream ports as needed.
    • USBx_CE is typically not used and can be left unconnected
    • USDx_ID should be grounded to enable host mode.
    • USBx_DRVVBUS should be connected to the enable of the 5V VBUS power source.
    • USBx_VBUS should be connected to the output of the 5V VBUS power source. It is also connected to the VBUS detect on the hub, which then allows the hub to selectively enable/disable typically through a power switch to each downstream port.

External Interrupt (EXTINTn)

  • This signal is active high for PG1.0 and active low for PG2.x. Boards designed to support all silicon revisions may want contain population options for both in case you move between different revisions of the AM335x during development. New designs are expected to use only PG2.1.
  • This signal connects directly to the Cortex A8 interrupt controller, which as a result makes this a level sensitive pin. It is recommended to consider using a GPIO signal instead of EXTINTn. The GPIO pins offer more flexibility with respect to polarity as well as the ability to be edge triggered.


  • While no series resistors are required for MII/RMII/RGMII, it is prudent include zero-Ohm stuff options for the TX and RX lines. Ideally, these option resistors should be as small as possible (0402 or smaller recommended) and should be placed as close to the transmitter as possible.


The following table describes what to do with each pin related to RTC functionality. Three use case scenarios are provided:

  • RTC-only mode: If you will be using the low power RTC-only mode. This use case allows low power operation of the AM335x by allowing only the RTC power supply to be ON while all the remaining supplies are OFF.
  • RTC timer functionality but no RTC-only mode: If you will be using the RTC feature but do not need RTC-only mode. This use case allows you to use the Real Time clocking features (eg, keeping time), but you do not need to support the low power RTC-only mode.
  • RTC feature disabled: If you will never use the RTC features. In this use case, the RTC functions are fully disabled.
Pin Function RTC-only mode RTC timer functionality
but no RTC-only mode
RTC feature disabled
VDDS_RTC 1.8 V power supply Always on RTC 1.8 V power supply any AM335x 1.8 V power supply3) any AM335x 1.8 V power supply3)
CAP_VDD_RTC RTC core voltage input/LDO output1) 1 uF decoupling capacitor to VSS VDD_CORE4) VDD_CORE4)
RTC_PWRONRSTn RTC power on reset input 1.8 V RTC power on reset2) 1.8 V PWRONRSTn 5) VSS
PMIC_POWER_EN PMIC power enable output PMIC power enable input No Connect No Connect
EXT_WAKEUP External wakeup input 1.8 V wakeup event signal VSS VSS
Datasheet(SPRS717J) power up sequencing Figure 6-2, 3, 4 Figure 6-5 Figure 6-6


  1. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
  2. If the internal RTC LDO is disabled,CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
  3. RTC_PWRONRSTn should be asserted for at least 1ms for internal RTC LDO output voltage stabilized when internal RTC LDO is enabled.
  4. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE.
  5. RTC_PWRONRSTn high level must be 1.8V.  It cannot be 3.3V.  If tied together with PWRONRSTn, both reset inputs high level must be 1.8V
  6. If using an external LVCMOS input for the 32 kHz clock it must be 1.8V amplitude since this pin is related to VDDS_RTC.

General Recommendations


As you are creating the schematics for your project here are a few things to consider.

Before you begin


Make sure you have the latest version of documentation, especially the data sheet and silicon errata.

TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important.

TIP: - on each device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata.

Pin out

  • Have you verified that your pin labels correspond to the correct pin numbers?
  • Have you verified that the power pins are connected to the correct supply rails?
  • Pullups/Pulldowns:
Internal pull-up/pull-down resistors are implemented with weak transistors. As the voltage present on the I/O pin varies the relative gate voltage to this weak transistor changes which will cause the effective pull-up/pull-down resistance to change. Therefore, internal resistors do not have a linear response like external resistors. The non-linearity along with process voltage and temperature variations require internal pull-up/pull-down resistors to be specified with a wide range of resistance or current sourcing/sinking.
The input current without a pull-up or pull-down turned on defines the input leakage without any current from internal pull resistors. The input current with a pull-up or pull-down turned on defines a combination of input leakage current and current required to force the internal pull resistors to the opposite voltage rail. For example, if an internal pull-up is turned on the value shown represents the total current required to pull the input to VSS.
When deciding what value of external resistor to use, you must consider the worst case combination of all internal leakage paths of all devices connected to a signal and make sure the external resistor is able to force these internal leakage paths to a potential greater than Vih min, or less than Vil max.

Critical Connections

Decoupling Capacitors

Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling.

PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply.

Refer to General Hardware Design/ BGA PCB Design/BGA Decoupling Wiki

Power Sequencing

Are all requirements being met in terms of the order, delays, etc. of the power supplies?


Make sure your input clock/crystal meets the data sheet requirements. For example:

  • Frequency
  • ESR for crystal
  • Load capacitance meets both the crystal’s and processor’s requirements
  • Crystal and caps placed physically close to processor
  • Double check proper voltage level for clock (some devices will use core voltage, others I/O voltage).
  • If there are any PLL configuration pins make sure they are set such that the resulting frequency is within device spec. Also, having alternate population options for those PLL pins could be handy.

OSC Internal Oscillator Clock source

The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components.

  • OSC Crystal Circuit Schematics

Clockckt v2.jpg

In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality:

Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms

However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs.

Please refer the below application note for calculation of Rs and RBais values:

Please refer the application note for the calculation of Rs and RBais values Crystek Application notes

Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the OMAPL1x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.


Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable!

A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets.

Also, you might want to have a reset button on your board as it can be helpful for development.

Boot modes

  • Double check that the boot configuration pins are set to the correct option.
  • It's highly recommended to have some population options to be able to easily change the reset mode. This can be handy in a variety of circumstances. For example, if you were doing a NOR flash boot and you ever accidentally put in some bad code you might end up in a scenario where you can't connect to the device with emulator because it's in a bad state, and you can't reprogram the flash as a result! Having an alternate boot mode can be a life saver!
  • Read carefully the initialization section in the Technical Reference Manual of your processor. We may have to deal with important information that can change your design. Look for which chip select is used by default, default clock setups, bus widths, wait states, supported booting devices, initial fetch address and interrupt vector addresses, default memory map and so on.
  • CAUTION: Be careful if anything is hooked up to these pins (i.e. if the pins are have multiple uses such as GPIO or other peripherals). You must make sure that the boot pins are at the proper levels when power-on reset occurs such that the correct values are latched in order for the device to boot correctly!

Pin Muxing

Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately.



  • Check that there are no unnecessary USB_DM or USB_DP connections that would form stubs.
  • Check that there is nothing on the DP/DM lines (except for possibly a USB 2.0 certified surge suppressor)
  • USB supports hot insertion and removal so it is very vulnerable to ESD resulting from this. External ESD protection like the TPD2E001 or TPD3E001 is recommended. For USB OTG the recommended ESD protection is the TPD4S012. Any USB 2.0 certified ESD protection chip is acceptable as long as the USB PCB routing guidelines are followed.

DDR2 Routing Checklist

DDR2/mDDR Routing Checklist

External Memory Interface (NOR/async)

The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly.


  • ~5K pull ups on both lines (only one set, or two sets of 10K pull ups) are recommended
  • Make sure all devices on a given I2C bus have unique addresses (often this is configurable through a pin to enable multiple of the same device)


This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:

  • TX ---> RX
  • RX <--- TX

Debug Considerations


This is something often done incorrectly which can severely impact your ability to develop code!

Signal Visibility

For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well.


Voltage Level Changes

Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later.

Signal Terminations

Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction.

For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption.

Ground Symbols

The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools.

Power Symbols

The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board.


This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.