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AM3517/05 GPMC Subsystem

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Features

The GPMC is a 16-bit external memory controller. The GPMC data access engine provides a flexible programming model for communication with all standard memories. The GPMC supports various accesses: 

  • Asynchronous read/write access
  • Asynchronous read page access (4, 8, 16 Word16)
  • Synchronous read/write access
  • Synchronous read/write burst access without wrap capability (4, 8, 16 Word16)
  • Synchronous read/write burst access with wrap capability (4, 8, 16 Word16)
  • Address/data-multiplexed access
  • Little- and big-endian access

 

The GPMC can communicate with a wide range of external devices:

  • External asynchronous or synchronous 8-bit wide memory or device
  • External asynchronous or synchronous 16-bit wide memory or device
  • External 16-bit nonmultiplexed device with limited address range (2 Kbytes)
  • External 16-bit address/data-multiplexed NOR flash device
  • External 8-bit and 16-bit NAND flash device
  • External 16-bit pseudo SRAM (pSRAM) device

The GPMC supports up to eight chip-select regions of programmable size, and programmable base addresses in a total address space of 1 Gbyte.

 

AM35x GPMC connections

This section shows the high level diagrams for connecting NAND and NOR flash memories to the GPMC.


8-bit NAND

The device does not provide the A0 byte address line required for random-byte addressable 8-bit wide device interfacing (for multiplexed and nonmultiplexed protocol). Hence, an 8-bit
device must be connected to the D[7:0] / gpmc_d[7:0] data bus (rather than D[15:8] / gpmc_d[15:8]) of the GPMC controller. This limits the use of 8-bit wide device interfacing to byte-alias access.

GPMC nand 8 connect.JPG

16-bit NAND

 GPMC nand 16 connect.JPG


16-bit NOR with external latch 

A typical NOR Flash device has a non-multiplexed interface.  Because the GPMC only supports 2KB for non-mux mode if you would like to interface a non-muxed NOR Flash with more than 2KB then an external latch can be added to the circuit to allow the GPMC to be set up in mux mode allowing the full addressable range.  In the below diagram we are interfacing a 1Gb NOR flash.  You can use the SN74ALVCH16374 latch.  It is a 16bit D-type flip flop. 

Note: If your NOR flash has a nADV pin (e.g. Numonyx Axcell P30) then most likely you do not need an external latch! Those devices already have an integrated latch which can be used directly. For this case you should see the section further down called "16-Bit address/data multiplexed memory".

GPMC NOR connect.JPG


16-bit NOR (2KB only)

Non-mux NOR interface (2KB only).  When the GPMC is in non-mux mode it forces A[26:11] pins to 1, so the device only had 2KB of addressable space (A[10:0]) GPMC NOR no latch2.JPG

16-Bit address/data multiplexed memory

This figure shows a connection between the GPMC and a 16-bit synchronous address/data-multiplexed external memory device.

GPMC 16b mux sync.JPG

Performance

Below is the Throughput achived with Writes and Reads between the GPMC and the LPDDR.

Initiator

Data Size 
(Bytes)

Achieved Throughput
(MB/sec)

GPMC Tx(Write) 156000 51.54
GPMC Rx(Read) 156000 39.21


FAQ

What is the max Frequency of the GPMC?

The GPMC max speed is 86MHz for the AM35x


Does the GPMC support NAND devices that require 4-bit ECC?

The AM35x GPMC supports 1, 4, and 8 bit BCH ECC detection.  The ROM code in the AM35x devices supports 1-bit Error Correction.  If a NAND device that requires 4-bit ECC, then the 4-bit correction must be done in software. 


Does the GPMC support non Address/Data multiplexed NOR memories?

Yes, but the GPMC only supports 2KB of addressable memory space when in non-mux mode.  If you would like to use a larger non-muxed NOR memory, they you can use an external latch to get the address un-muxed from the GPMC, but still maintain the full address space by keepint the AM37x device in mux mode.  Please see diagram above for the info on connecting a NOR memory with an external latch.


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