AM35x Overview

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Important Documentation

Block Diagram

Hardware Datsheet
Fig 1. AM35x Block Diagram
AM35x-OMAP35x-PSP 03.00.01.06 Feature Performance Guide
Fig 2. AM35x Software Block Diagram


 

Product Matrix

For a general overview of TI's ARM portfolio, see the ARM Portfolio Technical Overview Brochure.

Also take a look at the DSP & ARM MPU Selection Tool for help choosing a processor.

For a comparison between ARM9, ARM11 and Cortex-A8, take a look at this matrix.


AM3517 AM3505
Package Options ZER, ZCN
Cortex-A8 Processor 600 MHz
2D/3D Graphics Accelerator 110 MHz None


OMAP35x to AM35x Migration

Silicon Reference

Schematic Guidelines

Symbols, Footprints, and Simulation Models

Thermal Use Cases

Refer to appendix C of nFBGA Packaging application note for thermal modeling results.

SW Overview

Linux

Refer to the AM35x EVM Software Setup page for instructions on setting up the software.

Instructions for building Qt - A cross-platform application and user interface (UI) framework.

Windows

Coming soon: a Windows® Embedded CE (Windows CE) Board Support Package (BSP) and Software Development Kit (SDK) for AM35x.

This board support package (BSP) based on the Windows Embedded CE 6.0 R3 kernel and supporting advanced Sitara AM35x features including 3D graphics acceleration.


Windows Embedded CE BSP for AM35x - Architecture Win CE BSP for TI AM35x.png

QNX

Refer to QNX site for QNX BSP as well as release notes.

Peripheral Overview

Microprocessor Unit (MPU) Subsystem

The MPU subsystem integrates the following modules
ARM subchip

  • ARM® Cortex™-A8 core
    • ARM Version 7™ ISA: Standard ARM instruction set + Thumb®-2, Jazelle® RCT Java accelerator,
      and media extensions
  • NEON™ SIMD coprocessor (VFP lite + media streaming instructions)
  • Cache memories
    • Level 1: 32KB instruction and 32KB data—4-way set associative cache, 64 bytes/line
    • Level 2: see Section 1.5, AM/DM37x Family.
  • Interrupt controller (MPU IN TC) of 96 synchronous interrupt lines
  • Asynchronous interface with core logic
  • Debug, trace, and emulation features: ICE-Crusher, ETM, ETB modules.

For additional details on CortexA8 click here

Memory Management Units (MMU)

The AM35xx device contains three memory management units (MMU):

  • Microporocessor unit (MPU) MMU
  • PowerVR SGX core MMU
  • CAN Controller MMU

System Direct Memory Access (SDMA)

The System Direct Memory Access (SDMA), also called DMA4, performs high-performance data transfers between memories and peripheral devices without microprocessor unit (MPU) support during transfer.

Interrupt Controller (INTC)

The device has one interrupt controller (INTC) module, the MPU subsystem INTC (INTCPS). This module handles all MPU-related events, using Priority Threshold and Security Features. It communicates with the ARM Cortex-A8™ processor using a private local interconnect, and runs at half the speed of the processor.

Memory Subsystem

General-Purpose Memory Controller (GPMC)

The general-purpose memory controller (GPMC) is dedicated to interfacing external memory devices:

  • Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
  • Asynchronous, synchronous, and page mode (only available in non-muxed mode) burst NOR flash devices
  • NAND flash
  • Pseudo-SRAM devices
  • 1b, 4b, and 8b ECC Detection only. Please see the GPMC ECC article on how to use NAND Memories that require 4b and 8b ECC correction.

SDRAM Controller Subsystem (SDRC)

The SDRC subsystem module provides connectivity between the processor and external discrete DDR SDRAM.

The SDRC subsystem provides a high-performance interface to a variety of fast memory devices. It comprises two submodules:

  • The SDRAM Memory Scheduler (SMS), consisting of scheduler, security firewall, and virtual rotated frame-buffer (VRFB) modules.
  • EMIF (External Memory Interface).

AM3517/05 SDRC Subsystem

On-Chip Memory (OCM) Subsystem

The on-chip memory subsystem consists of two separate on-chip memory controllers, one connected to an on-chip ROM (OCM_ROM) and the other connected to an on-chip RAM (OCM_RAM). Each memory controller has its own dedicated interface to the L3 interconnect.

VPFE

The video processing subsystem (VPSS) includes a video processing front-end (VPFE) controller, which is the video input portion of the processor. The VPFE controller receives input video/image data from external capture devices and stores it to external memory.

POWERVR SGX™ Graphics Accelerator (SGX) - AM3517 only

The POWERVR SGX™ Graphics Accelerator (SGX) subsystem accelerates 3-dimensional (3D) graphics applications. The SGX subsystem is based on the SGX core from Imagination Technologies. SGX is a new generation of programmable PowerVR graphic cores. Targeted applications include feature phones, PDA, hand-held games, PND (portable navigation devices), MID (mobile Internet devices), automotive, and medical instrumentation.

The SGX graphics accelerator efficiently processes a number of various multimedia data types concurrently:

  • Pixel data
  • Vertex data

This is achieved using a multithreaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.

The SGX subsystem is connected by a 64-bit master and a 32-bit slave interface to the L3 interconnect. You can get getting started guide for Graphics SDK here.

Display Interface Subsystem

The display interface subsystem provides the logic to display a video frame from the memory frame buffer (either SDRAM or SRAM) on a liquid-crystal display (LCD) panel or a TV set. The display subsystem integrates the following elements:

  • Display controller (DISPC) module
  • Remote frame buffer interface (RFBI) module
  • Serial display interface (SDI) complex input/output (I/O) module with the associated phased-locked loop (PLL)
  • Display serial interface (DSI) complex I/O module and a DSI protocol engine
  • DSI PLL controller that drives a DSI PLL and high-speed (HS) divider
  • NTSC/PAL video encoder

The display controller and the DSI protocol engine are connected to the L3 and L4 interconnect; the RFBI and the TV out encoder modules are connected to the L4 interconnect.

For more information, refer to the Display Subsystem wiki.

Timers

The device includes several types of timers used by the system software, including 12 general-purpose timers (GP timers), three watchdog timers (WDTs), a 32-kHz synchronized timer.

The three WDTs are divided into a single secure WDT and two general-purpose WDTs. The WDTs are clocked with 32-kHz clocks. The 32-kHz synchronized timer, which is reset only at power up, provides the operating system with a stable timing source that stores the relative time since the last power cycle of the product. Finally, 12 GP timers, which are useful simply as basic timers, are included to generate time-stamp-based interrupts to the system software or to use as a source of pulse-width modulation (PWM) signals.

UART/IrDA/CIR Overview

The processor contains three universal asynchronous receiver/transmitter (UART) devices controlled by the microprocessor unit (MPU):

  • Three UART-only modules, UART1, UART2 and UART4 are pinned out for use as UART devices only UART1, UART2 and UART3 must be programmed by setting the UARTi.MDR1_REG[2:0] MODE_SELECT field to one of the three UART operating modes.
  • UART3, which adds infrared communication support, is pinned out for use as a UART, infrared data association (IrDA), or consumer infrared (CIR) device, and can be programmed to any available operating mode.

Inter-Integrated Circuit (I2C) Module

The device contains three multimaster high-speed (HS) inter-integrated circuit (I2C) controllers (I2CI modules, where I = 1, 2, 3), each of which provides an interface between a local host (LH), such as the MPU subsystem, and any I2C-bus-compatible device that connects through the I2C serial bus. External components attached to the I2C bus can serially transmit/receive up to 8 bits of data to/from the LH device through the 2-wire I2C interface.

Each multimaster HS I2C controller can be configured to act like a slave or master I2C-compatible device. Moreover, each multimaster HS I2C controller can be configured in serial camera control bus (SCCB) mode (the SCCB is a serial bus developed by Omnivision Technologies, Inc.) to act as a master on a 2-wire SCCB bus. Only multimaster HS I2C controllers I2C2 and I2C3 can be configured in SCCB mode to act as a master device on a 3-wire SCCB bus.

The device contains an additional master transmitter HS I2C interface (I2C4) in the PRCM module to perform dynamic voltage control and power sequencing. Texas Instruments Inc. provides a global solution with the device connected to power chips (TPS65023 device). For details about the TPS65023 device, contact your TI representative.

McSPI

The multichannel serial port interface (McSPI) is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. The McSPI modules differ as follows: SPI1 supports up to four peripherals, SPI2 and SPI3 support up to two peripherals, and SPI4 supports only one peripheral.

McBSP

The multi-channel buffered serial port (McBSP) provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips (digital base band), audio and voice codec (AIC23 device), etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.

The device provides five instances of the McBSP module.

HDQ/1-Wire Module

The HDQ/1-Wire module implements the hardware protocol of the master functions of the Benchmark HDQ and the Dallas Semiconductor 1-Wire® protocols. These protocols use a single wire for communication between the master (HDQ/1-Wire controller) and the slave (HDQ/1-Wire external compliant device).

The HDQ and 1-Wire module has a generic L4 interface and is intended to be used in an interrupt-driven fashion. The one-pin interface is implemented as an open-drain output at the device level. The HDQ operates from a fixed 12-MHz functional clock provided by the PRCM module. Only the MPU subsystem uses the HDQ/1-Wire module.

The main features of the HDQ/1-Wire module support the following:

  • Benchmark HDQ protocol
  • Dallas Semiconductor 1-Wire® protocol
  • Power-down mode

The HDQ/1-Wire module provides a communication rate of 5K bits/s over an address space of 128 bytes.

A typical application of the HDQ/1-Wire module is the communication with battery monitor (gas gauge) integrated circuits.

Multimedia Card/Secure Digital/Secure Digital I/O (MMC/SD/SDIO) Card Interface

The processor contains three multimedia card high-speed/secure data/secure digital I/O (MMC/SD/SDIO) host controller which provides an interface between a local host (LH) such as a microprocessor unit (MPU) or digital signal processor (DSP) and either MMC, SD memory cards, or SDIO cards and handles MMC/SD/SDIO transactions with minimal LH intervention.

The application interface manages transaction semantics. The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness.

The application interface can send every MMC/SD/SDIO command and either poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.

The application interface can read card responses or flag registers. It can also mask individual interrupt sources. All these operations can be performed by reading and writing control registers. The MMC/SD/SDIO host controller also supports two DMA channels.

In order to create a bootable SD/MMC card under Linux compatible with OMAP3 boot ROM, you'd have to set a special geometry in the partition table, which is done through the fdisk "Expert mode" as described here.

Universal Serial Bus (USB)

The AM35xx device includes a high-speed universal serial bus (USB) OTG controller and a high-speed USB host subsystem.

USB OTG port is built around the Mentor USB 2.0 OTG core (musbmhdrc)

  • Supports USB 2.0 peripheral at speeds HS (480 Mb/s) and FS (12 Mb/s)
  • Supports USB 2.0 Host or OTG at speeds HS (480 Mb/s), FS (12 Mb/s), and LS (1.5 Mb/s)
  • Supports all modes of transfers (control, bulk, interrupt, and isochronous)
  • Supports high bandwidth ISO mode
  • Supports 16 transmit (TX) and 16 receive (RX) endpoints including endpoint 0
  • Supports USB OTG extensions for session resume (SRP) and Host negotiation (HNP)
  • Includes a 32K endpoint FIFO RAM, and supports programmable FIFO sizes
  • Includes RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
  • Includes CDC Linux mode for accelerating CDC type protocols using short packet termination over USB
  • Included and RNDIS like mode for terminating RNDIS type protocols without using short packet termination for support of MSC applications
    • Connects to a standard charge pump for VBUS 5 V generation
    • DMA supports stall on buffer starvation & supports data buffer sizes up to 4M bytes
    • CPPI FIFO interface per TX/RX endpoint
  • The USB Host controller is a high-speed multiport USB2.0 host controller. It contains two independent, 3-port host controllers that operate in parallel:
    • The EHCI controller, based on the Enhanced Host Controller Interface (EHCI) specification for USB Release 1.0, is in charge of high-speed traffic (480M bit/s), over the ULPI/UTMI interface
    • The OHCI controller, based on the Open Host Controller Interface (OHCI) specification for USB Release 1.0a, is in charge of full-speed/low-speed traffic (12/1.5M bit/s, respectively), over a serial interface
  • Complies with the USB 2.0 standard for high-speed (480M bit/s) functions
  • USB 2.0 low-speed (1.5M bit/s) and full-speed (12M bit/s) over serial interface
  • High-speed (480M bit/s) operations over ULPI
  • Three downstream ports (3-port root hub)
  • Complies with EHCI (high-speed host controller)
  • Complies with OHCI (low-speed/full-speed host controller)
  • Supports suspend/resume and remote wakeup
  • Interface with ULPI PHYs (transceivers) on two ports
    • 12-pin/8-bit data single data rate (SDR) mode
    • 60-MHZ clock, generated by the host: ULPI "input" clocking mode

Note: The HS USB host subsystem only supports PHYs that can accept a 60 MHZ input clock. The HS USB host subsystem can only support the external charge pump of PHY (no support of internal charge pump for ULPI PHY).

General Purpose I/O (GPIO) Interface

The general-purpose interface combines six general-purpose input/output (GPIO) banks.

Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 192 (6 x 32) pins.

These pins can be configured for the following applications:

  • Data input (capture)/output (drive)
  • Keyboard interface with a debounce cell
  • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations.
  • Wake-up request generation in idle mode upon the detection of external events.

These modules do not include pad control (pull up/down control, open-drain feature).

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC subsystem module and is considered integral to the EMAC/MDIO peripheral.

The EMAC module is used to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol.

AM35x EMAC/MDIO Module

HECC

The CAN controller is available in two different implementations that are both fully compliant with the CAN protocol, version 2.0B. The two different CAN controller versions use the same CAN protocol kernel module to perform the basic CAN protocol tasks. Only the message controller differs between the two CAN controller versions.

Key features of the CAN module include:

  • Common CAN protocol kernel (CPK) to perform protocol tasks
  • Standard CAN controller (SCC) for standard CAN applications
    • Sixteen message-object acceptance-filtering
  • High-end CAN controller (HECC) for complex applications
    • Thirty-two message objects full-mask acceptance-filtering

AM3517 High-End Can Controller (HECC)


Development and Reference Designs

Development Boards

  • EVM - Details on the evaluation module (EVM) can be found through the TI website.

Power Companion Reference Design

Reference Designs

  • You can find schematics for the EVM from LogicPD's site after creating an account and registering your board.
  • You can find complete schematic and layout files for the open source Craneboard in the hardware section on craneboard.org.

Related End Equipments

These links provide block diagrams and design considerations for various products.

Training Material

Why AM35x - FAQ's

  • Pin for Pin compatible set of devices for design flexibility
  • Upto 30% reduction in system cost due to high integration
    • Memory Controller support DDR2/mDDR providing flexibility to choose memory
    • Integrated USB OTG PHY, EMAC Controller, CAN Controller with CortexA8 Core that can run upto 600 MHz.
    • 1.8 / 3.3 V dual voltage IO allows selection of 3.3 V IO thus avoiding additional level shifters & keeping the cost low.
    • Low power Industrial Application Processor, that doesn't require external cooling
    • Packages Offered
      • ZER(23x23, 1mm pitch) 1 mm ball pitch
      • ZCN(17x17, 0.65mm pitch) Via channel Routing package that allows customers to use .8 mm routing rules
  • How can I estimate Power required for my application using AM35x processors
  • How can I determine which product in AM35x family is best choice
    • Please click here to get product matrix describing different features supported by device
  • What are key care abouts for board design with AM35x
    • Please refer to AM35x Schematic Checklist for general checklist to ensure device connectivity as well as key items to be addressed. If you are using ZCN package this article will help you route your board in 4 layers. In addition you can use symbols & footprints for appropriate package from here.
  • Where can I get more details on Wireless LAN connectivity compatibility

Useful Links

AM3517 Schematic Checklist

AM35x Power Estimation Spreadsheet

DSP & ARM MPU Selection Tool

Sitara ARM Microprocessors Forum - Visit this site to ask questions and search for answers

AM35x Product family

Sitara Prodct line

Texas Instruments Sitara AM35x/OMAP35x unified BSP

Partnership between TI and Adeneo Embedded