AM35x Power Estimation Spreadsheet

From Texas Instruments Embedded Processors Wiki

Contents 1 Abstract 2 The Power Estimation Spreadsheet 3 Modeling Power for an Active Scenario 4 Using the Power Estimation Spreadsheet 4.1 Section A: High-Level System Configuration 4.2 Section B: Baseline Core Power 4.3 Section C: VDD_CORE (Modules Active Power) 4.4 Section D: FULL CHIP POWER TALLY 5 Important Notes and Limitations 6 References 7 Revision History

Download AM3517_PowerEstimationSpreadsheet_v1_03.zip here.

Abstract

This article discusses the power consumption of the Texas Instruments AM3517 high-performance, industrial applications processor. Power consumption on the AM3517 device is highly application-dependent, therefore a spreadsheet is provided to model power consumption for a user’s application and to present some measured scenarios. Version 1.x of the spreadsheet supports configurability of device core modules such as the ARM Cortex-A8 and most peripherals. The data in the accompanying spreadsheet represents measurements and estimates for strong units, which are indicative of the expected maximums of power consumption for production units. Thus, the spreadsheet values may be used for board thermal analysis and power supply design as a maximum long-term average.

The data presented in the Version 1.x power estimation spreadsheet are based on measurements performed on AM3517 revision 1.0 silicon, as well as estimates.

The Power Estimation Spreadsheet

Version 1.03 is the latest version of the AM3517 Power Estimation Spreadsheet.

The spreadsheet applies to AM3517 and AM3505 devices.

Modeling Power for an Active Scenario

Power consumption estimates in the spreadsheet are separated by the major modules of the device, so that their contribution can be gauged independently of each other. The options in the spreadsheet are intended to provide some flexibility in customizing the worst case power consumption estimate for a specific application.

Power consumption in the AM3517 device consists of:

• static power – due to leakage current, and dependent on temperature; and
• active power – due to transistor switching, and independent of temperature.

Version 1.x of the AM3517 Power Estimation Spreadsheet models temperature effects on device power consumption. The user is allowed to specify an ambient temperature to be used in the power estimate. This is used to scale the baseline power estimate in the spreadsheet, which consists of device static power and power consumption from interconnects and clock trees.

Active power consumption is the power that is consumed by portions of the AM3517 that are performing some processing. Active power is independent of temperature, but dependent on voltage and module activity levels. Version 1.x of the AM3517 Power Estimation Spreadsheet allows configuration of activity for some modules in the AM3517 device. For other modules, measured scenarios are provided for the module, and the user is expected to select the usage scenario most closely aligned to the intended application.

Using the Power Estimation Spreadsheet

The Version 1.x power estimation spreadsheet consists of 4 sections: tables A, B, C and D. Using the power estimation spreadsheet involves simply entering appropriate usage parameters. Cells that are designed for user input are white in color. To use the spreadsheet, simply configure the white cells to a value most closely aligned with your intended scenario. The spreadsheet will display the details of power consumption for the configuration selected.

Briefly, the purpose of each of the 4 sections is:

• Section A: configure the high-level system configuration such as ambient temperature, IO voltage and ARM clock frequency.
• Section B: baseline device power consumption due to static power, DPLLs, and L3 and L4 clock trees.
• Section C: active power of ARM subsystem component, peripherals and graphics accelerator.
• Section D: full chip power tally.

Section A: High-Level System Configuration

This section allows the user to set an ambient temperature (not junction temperature) between -20C and 85C, VDDSHV I/O voltage (1.8 V or 3.3 V) and ARM clock freq (500 MHz or 600 MHz).

Figure 1. Section A of AM3517 power estimation spreadsheet allows configuration of ambient temperature, IO voltages and ARM clock frequency.

For modules powered by the VDD_CORE rail is assumed with the configuration for voltage and interconnect clocks shown in Table 1 below.
Table 1. Voltage and Clock configurations.

Parameter	Value
VDD_CORE voltage	1.2V
ARM clock frequency	500/600MHz
CORE_CLK frequency	332MHz
L3_ICLK frequency	166MHz
L4_ICLK frequency	83MHz
SGX_ICLK frequency	110MHz
SDRC_CLK frequency	166MHz
GPMC_CLK frequency	83MHz
SYS_CLK frequency	26Mhz

The spreadsheet presents information for only the full-featured AM3517 device in AM35x family. However, since the spreadsheet breaks out the power consumption due to each module in the AM3517, estimate for the AM3505 can be obtained by choosing the “N/A” or “off” option for the module not present in the device under consideration. This will ensure active power from the non-applicable module is not included in the power tally. The device differences are summarized as follows:

• AM3517 (device with SGX)
• AM3505 (device without SGX)

Section B: Baseline Core Power

This section represents the static leakage power of the device as well as the power consumption of the DPLLs and clock trees as shown in Figure 2. Although the AM35x family provides many clock-gating features for reducing the idle time power consumption of unused portions of the chip, this spreadsheet does not support these power optimization features as it does not contain a PRCM model to capture and enforce any interdependencies among modules. The baseline core power section assumes clocks and power are turned on throughout the device all the time, and is not configurable.

Figure 2. Section B of the AM3517 Power Estimation Spreadsheet v1.0 presents the device baseline power (leakage, DPLLs, L3 and L4 interconnects and clock trees).

Section C: VDD_CORE (Modules Active Power)

This section is used to configure the activity on the ARM subsystem as shown in Figure 3. For each subsystem, a user can select a power profile and enter module utilization as a percentage.

Figure 3. Section C of the AM3517 Power Estimation Spreadsheet allows configuration of the ARM subsystem and peripherals for active power estimation.

For each module, a drop-down menu of measured and estimated power profiles is provided. Details of the power profiles follow.

• Cortex-A8 ARM subsystem:

1. N/A – no active power contribution.
2. Cortex-A8 + Neon (max estimation) – based on mA/MHz/V number for Cortex-A8 with Neon usage, obtained from design simulations.
3. Dhrystone standalone (Cortex-A8, measured) – based on measurements done while running Dhrystone 2.1 on the Cortex-A8.
   

• SGX (2D/3D graphics accelerator engine):

1. N/A – no active power contribution.
2. Rendering a 3D graphics frame (measured) – power measured on strong ES1.0 silicon for a test case involving continuous rendering of 1 frame from 3D graphics benchmark. SGX at 110MHz.
3. Estimated max – maximum power from design simulations.

• SDMA (system direct memory access controller):

1. N/A – no active power contribution.
2. 1-channel
3. 4-channels
   
4. Estimated max – maximum power from design estimates.

• SDRC (SDRAM controller):

1. N/A – no active power contribution.
2. Estimated max – maximum power from design estimates.

• GPMC (general purpose memory controller):

1. N/A – no active power contribution.
2. DMA Burst Write to Pseudo-SRAM over GPMC – power measured on strong ES1.0 silicon for a burst write over GPMC to external PSRAM device.
3. DMA Burst Read from Pseudo-SRAM over GPMC – power measured on strong ES1.0 silicon for a burst read over GPMC to external PSRAM device.
4. GPMC 50% Write, 50% Read, Pseudo-SRAM – 50% of 2 and 50% of 3 above.
5. Estimated max – maximum power from design estimates.

• DSS (display sub-system):

1. N/A – no active power contribution.
2. Single plane, 24bpp, PCLK 27 MHz
3. Single plane, 24bpp, PCLK 54 MHz
4. Single plane, 24bpp, PCLK 72 MHz
5. Three planes, 24bpp, PCLK 27 MHz
6. Three planes, 24bpp, PCLK 54 MHz
7. Three planes, 24bpp, PCLK 72 MHz
8. Estimated max – maximum power from design estimates.

• VPFE (Video Processing Front End sub-system):

1. N/A – no active power contribution.
2. 8bit BT.656 Capture
3. 16bit data capture
4. Estimated max – maximum power from design estimates.

• USB (universal serial bus):

1. N/A – no active power contribution.
2. Bulk Transfer
3. Isochronous Transfer
4. Suspend
5. Estimated max – maximum power from design estimates.

• 10/100 Mbit Ethernet MAC:

1. N/A – no active power contribution.
2. TX and RX
3. Estimated max – maximum power from design estimates.

• HECC (High-End CAN Controller):

1. N/A – no active power contribution.
2. Estimated max – maximum power from design estimates.

• MMC (multimedia card host controller) 1, 2 and 3 have the same set of power profile options:

1. N/A – no active power contribution.
2. Active
3. Estimated max – maximum power from design estimates.

• McBSP (multi-channel buffered serial port) 1, 2, 3, 4 and 5 have the same set of power profile options:

1. N/A – no active power contribution.
2. 16MHz, 16MB transfer – power measured on strong ES1.0 silicon while McBSP module transferring 16MB data in loopback mode at 16MHz.
3. 27MHz, 16MB transfer – power measured on strong ES1.0 silicon while McBSP module transferring 16MB data in loopback mode at 27MHz.
4. 83MHz, 16MB transfer – power measured on strong ES1.0 silicon while McBSP module transferring 16MB data in loopback mode at 83MHz.
5. Estimated max – maximum power from design estimates.

• UART (universal asynchronous receiver/transmitter) 1, 2 and 3 have the same set of power profile options:

1. N/A – no active power contribution.
2. 115.2kbps – power measured on strong ES1.0 silicon while UART module functional at 115.2kpbs baud rate.

• GPTIMERS (general purpose timers):

1. N/A – no active power contribution.
2. All on 32kHz clock – all GP timers enabled and running on 32kHz clock.
3. All on SYSCLK – all GP timers enabled and running on system clock.

• MISC. PERIPHERALS (other miscellaneous peripherals such as I2C, SPI and GPIO modules):

1. N/A – no active power contribution.
2. Estimated max – maximum power from design estimates.

Section D: FULL CHIP POWER TALLY

This section allows the user to obtain a power consumption estimate for the full chip. For each power supply rail available on the AM3517, a set of power profiles is provided in a drop-down menu.

Figure 4. Section D of the AM3517 Power Estimation Spreadsheet provides a full chip power consumption estimate.

Available power profiles for the various power rails on AM3517 are documented below.

• VDD_CORE:

1. Customized scenario above – sum of power for the ARM subsystem as configured in section C.
2. Standby

• VDDS_DPLL_MPU_USBHOST:

1. Baseline (see details above) – power as shown in Section B.
2. Estimated max – maximum power from simulations.
3. Standby

• VDDS_DPLL_PER_CORE:

1. Baseline (see details above) – power as shown in Section B.
2. Estimated max – maximum power from simulations.
3. Standby

• VDDS_SRAM_MPU:

1. Typical measured at room temp – measured power on ES1.0 silicon.
2. Estimated max – maximum power from simulations.
3. Standby

• VDDS_SRAM_CORE_BG:

1. Typical measured at room temp – measured power on ES1.0 silicon.
2. Estimated max – maximum power from simulations.
3. Standby

• VDDSOSC:

1. Typical measured at room temp – measured power on ES1.0 silicon.
2. Estimated max – maximum power from simulations.
3. Standby

• VDDSHV:

1. IO stress test at room temp (see IOConfig1 sheet) – measured power on ES1.0 silicon with IO Pads configured as shown in “IOConfig1” sheet in the xls file.
2. Estimated max – maximum power from simulations.
3. Standby (room temp, optimized IO config)

• VDDS:

1. IO stress test at room temp (see IOConfig1 sheet) – measured power on ES1.0 silicon with IO Pads configured as shown in “IOConfig1” sheet in the xls file.
2. Estimated max – maximum power from simulations.
3. Standby (room temp, optimized IO config)

• VDDA1P8V_USBPHY:

1. Off, 0V
2. Active, Bulk Transfer
3. Active, Isochronous Transfer
4. Active, Suspend
5. Estimated max – maximum power from simulations.
6. Standby

• VDDA3P3V_USBPHY:

1. Off, 0V
2. Active, Bulk Transfer
3. Active, Isochronous Transfer
4. Active, Suspend
5. Estimated max – maximum power from simulations.
6. Standby

• VDDA_DAC:

1. Off, 0V – powered off.
2. NTSC composite
3. NTSC s-video
4. PAL composite
5. PAL s-video
6. Estimated max – maximum power from simulations.
7. Standby

Important Notes and Limitations

The following notes and limitations apply to Version 1.x of the AM3517 Power Estimation Spreadsheet:

• Effect of temperature on static power is modeled via the ambient temperature input. A linear extrapolation is performed on measurements taken at ambient temperatures of -20°C, 25°C and 85°C.
  
• The power measurements and estimates provided for the IO supply rails (VDDS and VDDSHV) are for the ZCN package (0.65mm pitch BGA). These could vary on other packages and for different board configurations.
• The power consumption data are based on silicon measurements supplemented with estimates.
• It is up to the user to input reasonable utilization numbers for the MPU subsystems for the purposes of maximum power analysis. 90-100% loading on either subsystem is not realistic for most application scenarios.

References

1. OMAP3530 Power Consumption Summary Application Report (www.ti.com Literature Number SPRAB98).

Revision History

Date	Modification
3/11/10	Version 1.00. Initial version.
5/10/10	Version 1.01. ARM frequency has been changed to 600 MHz.
5/12/10	Version 1.02. Added ARM freq selection from 500 MHz and 600 MHz.
6/22/10	Version 1.03. VDDA3P3V_USBPHY selection in section D)has been unlocked. VDDSHV voltage selection has been implemented.

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