AM35x To AM335x Hardware Migration Guide
Content is no longer maintained and is being kept for reference only!
- 1 Introduction
- 2 Software Migration Guide
- 3 Basic Feature comparison
- 4 Module Comparison
- 4.1 Processors
- 4.2 External Memory Interfaces
- 4.3 Power, Reset, and Clock Management
- 4.4 Multimedia Hardware Components
- 4.5 Communication Interfaces
- 4.6 Timers
- 4.7 Misc
- 4.8 New interfaces in AM335x
- 4.9 Pin and package
This article documents the differences between the TI AM35x and the TI AM335x processors. Note AM35x is the ARM-only version of this processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.
The device folders are found at the following web pages:
Software Migration Guide
For more information on software migration, please see:
Basic Feature comparison
The table below shows a comparison of the basic features of the AM35x and the AM335x. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.
|Device Family|| AM3505 - CortexA8
AM3517 - CortexA8 with SGX 530
| AM3357/6/2 - CortexA8 |
AM3359/8/4 - CortexA8 with SGX 530
|Packages|| 491-pin BGA (ZCN), .65-mm Ball Pitch with VCA
484-pin PBGA (ZER), 1.0-mm Ball Pitch
| 284-pin nFBGA (ZCE), .65-mm Ball Pitch with VCA|
324-Pin nFBGA (ZCZ), .80-mm Ball Pitch Full Array
|Co-processors and Subsystems|
|ARM Processor|| Cortex-A8 up to 600MHz;
16K-Byte Instruction and Data Caches;
256K-Byte L2 Cache
| Cortex-A8 up to 1GHz; |
32K-Byte Instruction and Data Caches;
256K-Byte L2 Cache w/ECC
|Single Operating Point||Supported OPP: 50/100/120/SRTurbo|
|SGX530 3D Graphics Engine||Y||Y|
|SDRAM Controller|| SDRC;
16, 32-bit memory controller with 1G-Byte total address space
| EMIF; |
16-bit memory controller with 1G-Byte total address space
|SDRAM Memory Scheduler (SMS)||Y||N|
|General Purpose Memory Controller (GPMC)|| 1 GB total address space;
up to 8 chip selects;
ECC: 1-bit (Hamming) and 4-bit, 8-bit (BCH)
| 1 GB total address space; |
up to 7 chip selects;
ECC: 1-bit (Hamming) and 4-bit, 8-bit, 16-bit (BCH)
|Integrated Error Locator Module (ELM)||N||Y|
|Crypto hardware accelerators||N||Y|
|Camera ISP / VPFE||Y||N|
|Display||Display SubSystem (DSS)||LCD Controller|
|USB Host||1||not present|
|eMAC||10/100 Mbps||10/100/1000 Mbps|
|CAN / HECC||1||2|
|UART||4 (1 with IrDA)||6 (6 with IrDA)|
|GPIO||up to 186 pins||up to 128 pins|
|ADC/TS||not present||8ch 12bit|
|Power, Reset, and Clock Management|
|ETM & ETB||Y||Y|
|IEEE 1500 support||not present||Y|
|32-kHz Sync Timer||1||not present|
AM35x and AM335x are both based on the ARM Cortex-A8 processor. The table below shows a comparison between these two devices.
|ARM Processor||ARM Cortex™ A8||ARM Cortex™ A8|
|Operating Performance Points||OPP100||OPP50, OPP100, OPP120, SRTurbo|
|Operating Voltages||1.2V||.95V, 1.1V, 1.2V, 1.26V|
|Operating Frequencies||600 MHz||275MHz, 500MHz, 600MHz, 720MHz|
|L1 Instruction Cache||16 Kbytes||32 Kbytes|
|L1 Data Cache||16 Kbytes||32 Kbytes|
|L1 with SED||No||Yes|
|L2 Cache||256 Kbytes||256 Kbytes|
|L2 with ECC||No||Yes|
|ROM Size||132 Kbytes (80 KB Secure ROM and 32 KB of Public ROM)||176 Kbytes (128 KB Secure ROM and 48 KB of Public ROM)|
|RAM Size||N/A||64 Kbytes|
Note: Please refer to the AM35x and AM335x Datasheets for the latest OPP values.
The Neon Coprocessor is the same between the two devices.
AM335x integrates an ARM Cortex M3 core that manages entry and exit of various stand-by and deep-sleep modes.
AM35x does not contain a dedicated wake-up controller.
The Graphics Engine SGX530 is binary compatible between the two devices.
AM35x has 64KB RAM.
AM335x has 64KB RAM
External Memory Interfaces
General Purpose Memory Controller
The GPMC module is binary compatible between the two devices. AM35x supports up to 8 chip selects, and AM335x supports up to 7 chip selects. The main difference between the device is the ECC hardware mechanism, which is outside of the GPMC module.
AM35x supports 1-bit (Hamming) and 4-bit, 8-bit (BCH) hardware ECC.
AM335x supports 1-bit (Hamming) ECC and has a new Error Locator Module (ELM) to support 4-bit, 8-bit, or 16-bit (BCH) ECC.
SDRAM Memory Controller
The SDRAM Memory Controller is different between the two devices.
AM35x supports the SDRC Subsystem, providing a 16- or 32-bit interface to m-SDR and LPDDR. 32-bit LPDDR (or mDDR) is only supported up to a 166 MHz clock frequency. The SDRC Sybsystem includes a SDRAM memory scheduler (SMS) and a virtual rotated frame-buffer (VRFB) within the subsystem supports rotations of 0/90/180/270 degrees.
AM335x supports the EMIF, providing a 16-bit interface to mDDR (LPDDR1), DDR2, and DDR3 memories. The EMIF does not support Virtual Rotated Frame Buffer (VRFB) 0/90/180/270 degree rotation in hardware. The AM335x EMIF supports:
- mDDR: up to 200 MHz clock (400 MHz data rate),
- DDR2: up to 266 MHz clock (532 MHz data rate),
- DDR3: up to 303 MHz clock (606 MHz data rate)
Power, Reset, and Clock Management
Power Management Feature Comparison
|HW Provisions for Power Optimization/ Control||AM35x||AM335x|
| Operating Voltage-Frequencies (OPPs)
|| Single operating point
|| OPP50, OPP100, OPP120, SRTurbo |
| Adaptive Voltage Scaling
||Not supported|| Class 2B Smart Reflex,|
VDD_CORE & VDD_MPU can be scaled. VDD_RTC is Fixed.
| Logic State Retention
| Individually Switchable Power Domains
|| Single Power Domain
|| Full support for individually ON/OFF of Power Domains. Note, in RTC_Only mode even WAKEUP Domain can be OFF|
| Dynamically gating OFF of Clocks to one/more of groups of
modules (clock domains) when inactive to conserve power
| HW Auto Clock/Power Domain Dependency Management
|| Not Supported
|| Not Supported|
| Low Power Deep-Sleep State w/ Auto Wakeup
|| Not Supported
|| Wake on: GPIO0 bank, UART0, RTC, I2C0, DMTimer 1ms, USB Resume and TSC/ ADC Control events |
| RTC Only Cold State
|| Not Applicable
||Supported. System includes 32KHz Osc integrated with alarm/wake signaling interface w/ PMIC.|
| Splitting Of Primary Voltage Supply Rails
||VDD_CORE, VDD_MPU*, VDD_RTC|
- * On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.
The following tables compare the power supplies for AM35x and AM335x:
|vdds_sram_mpu||MPU SRAM LDO||1.8V|
|vdds_sram_core_bg||Core SRAM LDO and BandGap||1.8V|
|vdds_dpll_mpu_usbhost||MPU and USBHOST DPLL||1.8V|
|vdds_dpll_per_core||Peripherals and core DPLLs||1.8V|
|vdda_dac||DAC power supply||1.8V|
|vdda3P3V_USBPHY||3.3V USB transceiver||3.3V|
|vdda1P8V_USBPHY||1.8V USB transceiver||1.8V|
|vddshv||3.3-/1.8-V power supply||1.8V / 3.3V|
|vdds||1.8V power supply||1.8V|
* Note: Please refer to the AM35x Datasheet for the latest values.
|VDD_MPU *||MPU domain||0.95V - 1.26V|
|CAP_VDD_RTC||RTC domain input/LDO output||1.1V|
|VDDS_DDR||DDR IO domain (DDR2 / DDR3)||1.8V / 1.5V|
|VDDS||Dual voltage IO domains||1.8V|
|VDDS_SRAM_CORE_BG||Core SRAM LDOs, Analog||1.8V|
|VDDS_SRAM_MPU_BB||MPU SRAM LDOs, Analog||1.8V|
|VDDS_PLL_DDR||DPLL DDR, Analog||1.8V|
|VDDS_PLL_CORE_LCD||DPLL Core and LCD, Analog||1.8V|
|VDDS_PLL_MPU||DPLL MPU, Analog||1.8V|
|VDDS_OSC||System oscillator IOs, Analog||1.8V|
|VDDA1P8V_USB0||USB PHY, Analog, 1.8V||1.8V|
|VDDA1P8V_USB1||USB PHY, Analog, 1.8V||1.8V|
|VDDA3P3V_USB0||USB PHY, Analog, 3.3V||3.3V|
|VDDA3P3V_USB1||USB PHY, Analog, 3.3V||3.3V|
|VDDSHV1||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV2 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV3 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV4||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV5||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV6||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV1||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV2 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV3 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV4||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV5||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV6||Dual Voltage IO domain (3.3-V operation)||3.3V|
|DDR_VREF||DDR SSTL/HSTL reference input (DDR2/DDR3)||0.50*VDDS_DDR|
|USB0_VBUS||USB VBUS comparator input|
|USB1_VBUS||USB VBUS comparator input|
|USB0_ID||USB ID input||1.8V|
|USB1_ID||USB ID input||1.8V|
* Note: These voltage rails are not available in the 13x13 package.
Clocks and PLLs
|sys_xtalin/out||High Frequency Input Clock||26 MHz|
|sys_altclk||Alternative Input Clock||48 MHz or 54 MHz|
|sys_32K||Low Frequency Input Clock||32 KHz|
|CLK_M_OSC||Master Oscillator||19.2, 24, 25, 26 MHz|
|CLK_32KHZ||Divide down of PER PLL output (PLL uses Master Osc)||32768 Hz Precise|
|CLK_RC_32KHZ||Internal RC Oscillator||16 - 60 kHz|
|CLK_32K_RTC||External 32768 Hz crystal with internal 32K Osc or external 32768 Hz clock||32768 Hz Precise|
The AM35 has the option to obtain the 32KHz clock from an external oscillator or from the HS system clock using a fixed divider.
The AM335x has the option to obtain the 32KHz clock from the high frequency 20MHz clock using an internal RTCDIVDER. If this is used, an external 32KHz clock source is not necessary. The 32KHz provides a clock for the following modules:
AM35x has the following PLLs, all driven by the HF clock:
- DPLL1 - MPU
- DPLL3 - Core
- DPLL4 - Peripherals
- DPLL5 - Peripherals 2
AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):
- Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRUSS IEP, Debugss
- Peripheral (Per) PLL - for USB PHY, PRUSS UART, MMC/SD, SPI, I2C, UART
- MPU PLL - for MPU Subsystem (includes Cortex A-8)
- Display PLL - for LCD Pixel Clock
- DDR PLL - for EMIF
The available bootmodes for AM35x and AM335x are shown in the table below.
|Y||Y||NOR|| This mode allows booting from XIP booting devices, such as NOR flash memories. |
For AM35x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x16 is supported. The GPMC is clocked at 48MHz.
For AM355x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 50MHz.
|Y||Y||NAND|| This mode starts downloading code from an NAND memory. |
For AM35x, NAND flash (from 64Mbit, or 8Mbyte) from should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 48MHz.
For AM335x, NAND flash (from 512Mbit, or 64Mbytes)should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 50MHz.
|N||Y||SPI|| This mode starts downloading code from an SPI EEPROM or SPI Flash. |
For AM335x, the external SPI device should be connected to the SPI0 chip select 0 signal (SPI0_CS0).
|Y||Y||UART|| In this mode, the UART sends a BOOTME request to the UART peripheral and waits for a response along with code from a host processor. |
Both AM35x and AM335x must be booted using a baud rate of 115200. AM35x can only boot from UART3. AM335x can only boot from UART0.
|Y||Y||MMCSD|| This mode starts booting code from an MMC/SD Controller. |
For AM35x, the MMC/SD cards should connected to either MMC1 or MMC2. 1.8V or 3.3V I/O voltage is supported on MMC1 and MMC2. (External transceiver mode on MMC2 is not supported.) The supported clock frequencies are up to 400 kHz (identification mode) and 20 MHz (data transfer mode).
For AM335x, the MMC/SD cards should connected to either MMC0 or MMC1. 1.8V or 3.3V I/O voltage is supported on MMC0, and only 1.8V I/O voltage is supported on MMC1. The supported clock frequencies are up to 400 kHz (identification mode) and 10 MHz (data transfer mode).
|N||Y||EMAC|| This mode starts booting code from the EMAC port. |
For AM335x, EMAC boot uses the CPGMAC port 1 of the device.
|Y||N||DiskOnChip||In this mode, the DiskOnChip is connected just like a regular NOR device.|
|Y||N||HS USB||In this mode, the ROM code boots from a USB interface.|
Multimedia Hardware Components
AM35x has a display subsystem (DSS) that supports the following resolutions: XGA, WXGA, SXGA+, and HD 720p.
AM335x has a simple LCD controller with no preprocessing operations such as preview, overlay, blending, resizing, etc. The AM335x LCD controller supports up to WXGA resolution.
The AM35x and AM335x devices support different versions of industry standards (shown below).
|Spec Compliance|| MMC v4.2
SD card v1.0
| MMC v4.3|
SD card v2.0
|Data width *||8-bit (MMC1/2/3)||8-bit (MMC0/1/2)|
|Max Clock Rate|| 48MHz (MCC),
| 48MHz (MCC),|
The main differences between the two devices with respect to USB is the integrated PHYs and the more flexible operation in the AM335x.
The AM35x requires an external PHY with both the USB-OTG and USB1-3 host ports. Also, the USB1-3 ports are only capable of host mode operation, at either high speed or full speed mode (not both).
The AM335x has 2 USB ports capable of host and OTG operations. Both ports have an integrated PHY.
The I2C ports are binary compatible same between the two devices.
AM35x supports 3 general I2C ports. The I2C ports can support up to 3.4Mbps high speed transmissions, along with the usual 100/400Kbps operation.
AM335x supports 3 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.
The UART modules on both devices are functionality compatible with the TL16C750 (and TL16C550) UART. The primary differences between devices are the number of UARTs and supported capabilities.
AM35x has 4 UARTs. Only UART3 has IrDA capabilities.
AM335x has 6 UARTs, all of which support IrDA, CIR, and flow control. Full modem control is only available on 1 UART instance. AM335x allows 1 instance of UART rx/ tx lines to be muxed with USB DP/ DM lines.
AM35x supports a High-End CAN Controller (HECC). The HECC is compliant with CAN 2.0b and supports 32 message objects for full-mask acceptance-filtering.
AM335x supports two (2) DCAN controllers. The DCAN is compliant with CAN 2.0b and supports 64 message objects.
AM35x has 5 McBSP ports and no McASP ports. AM335x has no McBSP ports and 2 McASP ports.
The McASP is a superset of the McBSP. It is suggested to use the McASP ports for McBSP functionality. Note the McASP ports on AM335x have less buffers for internal FIFO and audio loopback and no sidetone support.
The module does not exist on AM335x. It is suggested to use either I2C or GPIO for this type of functionality (eg, battery monitor).
The GPTimers on both devices are binary compatible.
AM35x has 11 32-bit GPTimers. Three GPTimers (GPTIMER1, GPTIMER2, and GPTIMER10) support 1-ms tick with 32,768 Hz functional clock generated. Only 4 GPTimers (GPT_8 - GPT_11) are pinned out.
AM335x supports seven (7) 32-bit GPTimers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 4 GPTimers (DMTIMER4 - DMTIMER7) are pinned out.
Both AM35x and AM335x have 1 32-bit Watchdog Timer.
32-kHz Sync Timer
The 32-kHz sync timer does not exist on AM335x.
AM35x supports 186 GPIO pins. The GPIO signals are divided into 6 banks, each supporting 32 GPIOs. Note only 186 of these GPIO signals are pinned out. Each bank supports two interrupts.
AM335x supports 4 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts.
New interfaces in AM335x
The following are new interfaces in the AM335x device that do not exist in AM35x. Any details about these interfaces can be found in the Technical Reference Manual for AM335x.
- PRUSS - Programmable Real-time Unit SubSystem
Pin and package
The AM35x and the AM335x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM35x and the AM335x devices.
|Device||Size (mm)||Pitch (mm)||No. of Pins||Package Designator|
|AM35x||17 x 17 mm||0.65 mm, with VCA||491||BGA (ZCN Suffix)|
|23 x 23 mm||1.00 mm top||484||PBGA (ZER Suffix)|
|AM335x||13 x 13 mm||0.65 mm, with VCA||298||s-PBGA (ZCE Suffix)|
|15 x 15 mm||0.80 mm||324||s-PBGA (ZCZ Suffix)|