AM387x To AM335x Hardware Migration Guide
- 1 Introduction
- 2 Software Migration Guide
- 3 Basic Feature comparison
- 4 Module Comparison
- 4.1 Processors
- 4.2 External Memory Interfaces
- 4.3 Power, Reset, and Clock Management
- 4.4 Multimedia Hardware Components
- 4.5 Communication Interfaces
- 4.6 Timers
- 4.7 Misc
- 4.8 New interfaces in AM335x
- 4.9 Pin and package
This article documents the differences between the TI AM387x processor and the TI AM335x processor. Note AM387x is the ARM-only version of this processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.
The device folders are found at the following web pages:
Software Migration Guide
For more information on software migration, please see:
Basic Feature comparison
The figures and table below show a comparison of the basic features of the AM387x and the AM335x. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.
|Device Family|| AM3872 - CortexA8
AM3874 - CortexA8 with SGX 530
| AM3357/6/2 - CortexA8 |
AM3359/8/4 - CortexA8 with SGX 530
|Packages||684-Pin BGA Package (CYE), 0.8-mm Ball Pitch With Via Channel™ (VCA)|| 284-pin nFBGA (ZCE), .65-mm Ball Pitch with VCA|
324-Pin nFBGA (ZCZ), .80-mm Ball Pitch Full Array
|Co-processors and Subsystems|
|ARM Processor|| Cortex-A8 up to 1GHz;
32K-Byte Instruction and Data Caches;
512K-Byte L2 Cache
| Cortex-A8 up to 720MHz; |
32K-Byte Instruction and Data Caches;
256K-Byte L2 Cache w/ECC
|Supported OPP: 50%/100%/120%/166%||Supported OPP: 50%/100%/120%/SRTurbo|
|Graphics Engine||SGX530 3D, 200 MHz||SGX530 3D, 200 MHz|
|mDDR/DDR2/DDR3 Controller|| Dual 32-bit LPDDR/DDR2/DDR3 SDRAM Interface
Supports up to LPDDR-400, DDR2-800, and DDR3-800
Total 2 GB Total Address Space
Dynamic Memory Manager (DMM)
| Single 16-bit LPDDR/DDR2/DDR3 SDRAM Interface |
Supports up to LPDDR-400, DDR2-532, DDR3-606
Total 1 GB Total Address Space
|On Chip Memory (OCMC)||128KB||64KB|
|Crypto hardware accelerators||N||Y|
|Camera ISP||Imaging SubSystem (ISS)||N|
|Display||HD Video Processing SubSystem (HDVPSS)||LCD Controller|
|USB OTG||Two (2) USB 2.0 High Speed ports with integrated PHY||Two (2) USB 2.0 High Speed ports with integrated PHY (13 x 13 Package has only one USB port)|
|eMAC||2 (10/100/1000 Mbps)||2 (10/100/1000 Mbps)|
|UART||6 (all with IrDA)||6 (all with IrDA)|
|GPIO||4 banks||4 banks|
|SATA Controller||Y||not present|
|Power, Reset, and Clock Management|
|ETM & ETB||Y||Y|
|IEEE 1500 support||Y||Y|
AM387x and AM335x are both based on the ARM Cortex-A8 processor. The table below shows a comparison between these two devices.
|ARM Processor||ARM Cortex™ A8||ARM Cortex™ A8|
|Operating Performance Points||OPP50, OPP100, OPP120, OPP166||OPP50, OPP100, OPP120, SRTurbo|
|Operating Voltages||.95V, 1.1V, 1.2V, TBD||.95V, 1.1V, 1.2V, 1.26V|
|Operating Frequencies||300MHz, 600MHz, 720MHz, 800MHz/ 1000MHz||275MHz, 500MHz, 600MHz, 720MHz|
|L1 Instruction Cache||32 Kbytes||32 Kbytes|
|L1 Data Cache||32 Kbytes||32 Kbytes|
|L1 with SED||No||Yes|
|L2 Cache||512 Kbytes||256 Kbytes|
|L2 with ECC||No||Yes|
|ROM Size||176 Kbytes||176 Kbytes|
|RAM Size||64 Kbytes||64 Kbytes|
Note: Please refer to the AM387x and AM335x Datasheets for the latest OPP values.
The Neon Coprocessor is the same between the two devices.
The SGX530 3D Graphics Engine is the same between both devices.
The main differences between the two devices with respect to eDMA are the number of TPTCs supported and the TPTC parameters.
AM387x eDMA supports 1 Third Party Channel Contoller (TPCC) and 4 Third Party Transfer Controllers (TPTC). The TPTC FIFO size is 1024 bytes and the address width for internal FIFOs is 6.
AM335x eDMA supports 1 Third Party Channel Contoller (TPCC) and 3 Third Party Transfer Controllers (TPTC). The TPTC FIFO size is 512 bytes and the address width for internal FIFOs is 5.
AM387x has 128KB RAM.
AM335x has 64KB RAM.
External Memory Interfaces
General Purpose Memory Controller
The GPMC module is binary compatible between the two devices. AM387x supports 8 chip selects. AM335x supports 7 chip selects.
The ELM (ECC H/W mechanism) is binary compatible between the two devices.
DDR Memory Controller
AM387x supports a dual 32-bit LPDDR/DDR2/DDR3 SDRAM Interface, with up to LPDDR-400, DDR2-667, and DDR3-667. Up to eight devices and 2 GB (total) of address space are supported. The Dynamic Memory Manager (DMM) implements a Tiling and Isometric Lightweight Engine for Rotation (TILER), which supports 0/90/180/270 degree rotation in hardware.
AM335x supports a single 16-bit LPDDR (mDDR)/DDR2/DDR3 SDRAM Interface, with up to LPDDR-400, DDR2-532, and DDR3-606. Up to seven devices and 1 GB (total) of address space are supported. 0/90/180/270 degree rotation is not supported hardware.
Power, Reset, and Clock Management
Operating Performance Points
Note: Please refer to the AM387x Datasheet for the latest OPP values.
Note: Please refer to the AM335x Datasheet for the latest OPP values.
The following table compares the power supplies for AM387x and AM335x:
|DVDD||I/O, standard pins||1.8V/3.3V|
|DVDD_GPMC||I/O, GPMC pin group||1.8V/3.3V|
|DVDD_GPMCB||I/O, GPMCB pin group||1.8V/3.3V|
|DVDD_SD||I/O, SD pin group||1.8V/3.3V|
|DVDD_C||I/O, C pin group||1.8V/3.3V|
|DVDD_M||I/O, M pin group||1.8V|
|DVDD_DDR, DVVD_DDR||I/O, DDR and DDR||1.8V/1.5V|
|VDDA_USB_3P3||I/O, Analog, USB 3.3V||3.3V|
|VDDA_1P8, VDDA_x_1P8||I/O, Analog||1.8V|
|Vrefsstl_ddr[x]||IO Reference Voltage||0.50*DVDD_DDR[x] V|
|USBx_VBUSIN||USBx VBUS Comparator Input||5V|
|VDD_MPU *||MPU domain||0.95V - 1.26V|
|CAP_VDD_RTC||RTC domain input/LDO output||1.1V|
|VDDS_DDR||DDR IO domain (DDR2 / DDR3)||1.8V / 1.5V|
|VDDS||Dual voltage IO domains||1.8V|
|VDDS_SRAM_CORE_BG||Core SRAM LDOs, Analog||1.8V|
|VDDS_SRAM_MPU_BB||MPU SRAM LDOs, Analog||1.8V|
|VDDS_PLL_DDR||DPLL DDR, Analog||1.8V|
|VDDS_PLL_CORE_LCD||DPLL Core and LCD, Analog||1.8V|
|VDDS_PLL_MPU||DPLL MPU, Analog||1.8V|
|VDDS_OSC||System oscillator IOs, Analog||1.8V|
|VDDA1P8V_USB0||USB PHY, Analog, 1.8V||1.8V|
|VDDA1P8V_USB1||USB PHY, Analog, 1.8V||1.8V|
|VDDA3P3V_USB0||USB PHY, Analog, 3.3V||3.3V|
|VDDA3P3V_USB1||USB PHY, Analog, 3.3V||3.3V|
|VDDSHV1||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV2 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV3 *||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV4||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV5||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV6||Dual Voltage IO domain (1.8-V operation)||1.8V|
|VDDSHV1||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV2 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV3 *||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV4||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV5||Dual Voltage IO domain (3.3-V operation)||3.3V|
|VDDSHV6||Dual Voltage IO domain (3.3-V operation)||3.3V|
|DDR_VREF||DDR SSTL/HSTL reference input (DDR2/DDR3)||0.50*VDDS_DDR|
|USB0_VBUS||USB VBUS comparator input|
|USB1_VBUS||USB VBUS comparator input|
|USB0_ID||USB ID input||1.8V|
|USB1_ID||USB ID input||1.8V|
* Note: These voltage rails are not available in the 13x13 package.
|DEV_CLKIN||High Frequency Input Clock||20MHz|
|AUX_CLKIN||Auxiliary Input Clock for Audio and/or Video PLLs||20MHz-30MHz|
|RCOSC32K||Low Frequency Input Clock||32KHz|
|SERDES_CLK||Optional Clock Source for SATA,EMAC,PCIe||32KHz|
|CLK_M_OSC||Master Oscillator||19.2, 24, 25, 26 MHz|
|CLK_32KHZ||Divide down of PER PLL output (PLL uses Master Osc)||32768 Hz Precise|
|CLK_RC_32KHZ||Internal RC Oscillator||16 - 60 kHz|
|CLK_32K_RTC||External 32768 Hz crystal with internal 32K Osc or external 32768 Hz clock||32768 Hz Precise|
The AM387x has the option to obtain the 32KHz clock from the high frequency 20MHz clock using an internal RTCDIVDER. If this is used, an external 32KHz clock source is not necessary. The 32KHz provides a clock for the following modules:
AM387x has the following PLLs. All of these can be individually driven by either DEV or AUX input clocks:
- PLL_ARM - for Cortex A8
- PLL_SGX - for SGX530 Graphics Controller
- PLL_L3 - for L3/L4 Interconnect, EDMA, MMU, GPMC, McASP, McBSP, UART3/4/5
- PLL_DDR - for DDR
- PLL_HDVPSS - for HD Video Processing SubSystem
- PLL_USB - for USB0/1,SPI,I2C,UART0/1/2,HDMI
- PLL_AUDIO - for McASP0/1/2,MCBSP CLKS,HDMI I2S
- PLL_MEDIACTL - for Imaging SubSystem and Media Controller (ARM Cortex-M3 processor for HDVPSS and ISS)
- PLL_VIDEO0/1/2 - for HDVPSS VENC, HDMI
AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):
- Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRUSS IEP, Debugss
- Peripheral (Per) PLL - for USB PHY, PRUSS UART, MMC/SD, SPI, I2C, UART
- MPU PLL - for MPU Subsystem (includes Cortex A-8)
- Display PLL - for LCD Pixel Clock
- DDR PLL - for EMIF
Power Management Feature Comparison
|HW Provisions for Power Optimization/ Control||AM387x||AM335x|
| Individually Switchable Power Domains
|| Limited Support for Individual Power Domain ON/OFF -- ISS, DSS, SGX
|| Full support for Individual Power Domain ON/OFF: VDD_MPU, VDD_CORE, VDD_PER, VDD_SGX and SRAMs. In RTC_Only mode, even WAKEUP Domain can be OFF'd|
| Dynamically gating OFF of Clocks to one/more of groups of
modules (clock domains) when inactive to conserve power
| Operating Voltage-Frequencies (OPPs)
|| OPP50, OPP100, OPP120
|| OPP100(VDD_MPU, VDD_CORE), OPP50(VDD_MPU, VDD_CORE), OPP120 (VDD_MPU)|
| Adaptive Voltage Scaling
|| Class 2B Smart Reflex,
VDD_CORE, VDD_MPU, Domains
| Class 2B Smart Reflex,|
VDD_CORE & VDD_MPU can be scaled. VDD_RTC is Fixed.
| SRAM memory retention
|| Only L3 OCMC RAM
|| All onchip SRAMs|
| HW Auto Clock/Power Domain Dependency Management
|| Not Supported|
|Low Power Deep-Sleep State w/ Auto Wakeup|| Not Supported
|| GPIO0 bank, UART0, RTC, I2C0, DMTimer 1ms, USB Resume and TSC/ ADC Control events |
|RTC Only Cold State|| Not Applicable
||Supported. System includes 32KHz Osc integrated with alarm/wake signaling interface w/ PMIC.|
| Splitting Of Primary Voltage Supply Rails
|| VDD_CORE, VDD_MPU
||VDD_CORE, VDD_MPU*, VDD_RTC|
- * On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.
|Y||Y||NOR|| This mode allows booting from XIP booting devices, such as NOR flash memories. |
For AM387x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_CS. GPMC_CS is mapped to address 0x0800_0000. A data bus width of x16 is supported. The GPMC is clocked at 55MHz.
For AM355x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 50MHz.
|Y||Y||NAND|| This mode starts downloading code from an NAND memory.|
For AM387x, NAND flash (from 512Mbit, or 64Mbyte) from should be connected to the GPMC peripheral on GPMC_CS. GPMC_CS is mapped to address 0x0800_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 55MHz.
For AM335x, NAND flash (from 512Mbit, or 64Mbytes)should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x16 is supported. The GPMC is clocked at 50MHz.
|Y||Y||SPI|| This mode starts downloading code from an SPI EEPROM or SPI Flash.
For both AM387x and AM335x, the SPI device should be connected to the SPI0 peripheral on CS0.
|Y||Y||UART|| In this mode, the UART sends a BOOTME request to the UART peripheral and waits for a response along with code from a host processor.
Both AM387x and AM335x must be booted using a baud rate of 115200. Both devices can only boot from UART0.
|Y||Y||MMCSD|| This mode starts booting code from an MMC/SD Controller. |
For AM387x, the MMC/SD cards should connected to MMC1. 1.8V or 3.3V I/O voltage is supported on MMC1.
For AM335x, the MMC/SD cards should connected to either MMC0 or MMC1. 1.8V or 3.3V I/O voltage is supported on MMC0, and only 1.8V I/O voltage is supported on MMC1.
|Y||Y||EMAC|| This mode starts booting code from the EMAC port. |
For AM387x, EMAC boot uses the CPGMAC port 0 of the device.
For AM335x, EMAC boot uses the CPGMAC port 1 of the device.
|Y||N||PCIe||This mode supports PCIe client mode boot and ROM code opens up the OCMC RAM to the PCIe Host. In this bootmode Host will copy boot code directly into OCMC RAM.|
Multimedia Hardware Components
A camera subsystem is not supported on AM335x.
AM387x has a display subsystem (DSS) with a video image coprocessor (HD-VICP) that supports up to HD 1080p.
AM335x has a simple LCD controller with no preprocessing operations such as preview, overlay, blending, resizing, etc. The AM335x LCD controller supports up to WXGA resolution.
The AM335x MMC/SD interface is an upgraded version from the module in AM387x.
|Spec Compliance|| MMC v4.3
SD Phys Layer v2.0
SD card v2.0
| MMC v4.3|
SD Phys Layer v3.0
SD card v2.0
|Data Width *||8-bit (SD0/1/2)||8-bit (MMC0/1/2)|
|Max Clock Rate|| 48MHz (MCC),
| 48MHz (MCC),|
* Note the supported data width is subject to pinmux constraints.
The AM335x USB interface is an updated version of the module in AM387x. Updates to the USB subsystem with respect to AM387x are listed below:
- Added Infinite mode support in XDMA
- Double packet buffering support for both TX/RX
- Added CPPI 4.1 DMA streaming mode support
- Added subword accesses to USBSS memory mapped registers
- Added Tx Endpoint FIFO Empty interrupt: TX_FIFO[15:0]. This signal indicates when the TX data transmission is completed on the USB interface. TX_FIFO interrupt is to be used with the CPPI packet completion flag. Setting a CPPI packet with the packet completion flag will generate the TX_FIFO when the transmit endpoint FIFO is empty after transmission.
The I2C ports are binary compatible between the two devices.
AM387x supports 4 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.
AM335x supports 3 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.
Both devices have six UARTs, which all support IrDA and flow control. Both devices incorporate dual 64 byte FIFOs for received and transmitted data.
On AM387x only UART0 supports full modem control. UART0/1/2 support up to 3.6864 Mbps. UART3/4/5 support up to 12 Mbps.
On AM335x only UART1 supports full modem control. All UARTs support a maximum baud rate of 3.6864 Mbps.
The CAN ports are binary compatible same between the two devices. Both AM387x and AM335x support 2 instances of CAN 2.0B.
AM387x has six McASP ports and one McBSP port. McASP0/1 support up to 10 McASP serializers, and McASP2/3/4/5 support up to 4 McASP serializers.
AM335x has two McASP ports and no McBSP ports. McASP0/1 support up to 4 McASP serializers.
- Note McASP is a superset of McBSP, so it is suggested to use McASP for McBSP functionality.
Real-Time Clock (RTC)
The AM335x RTC is an updated version of the module in AM387x. Updates to the AM335x RTC subsystem with respect to AM387x are listed below:
- Replaced software reset with RTC_PWRONRSTn (power on reset) input pin (ball B7 for 13 x 13 package, B5 for 15 x 15 package)
- Only assert when RTC has lost power
- De-assert when RTC voltage > Vmin
- Remains de-asserted during normal operations
- The AM335x RTC subsystem includes an integrated 32KHz oscillator, while the AM387x RTC subsystem does not—its clock is sourced from an external pin.
- Added new Power Management IC (PMIC) control logic and PMIC_PWR_ENABLE output pin, which can be used to enable/disable an external PMIC. See TRM for more information.
- Added external wakeup input pins EXT_WAKEUP[3:0]. See TRM for more information.
- Replaced software reset with RTC_PWRONRSTn (power on reset) input pin (ball B7 for 13 x 13 package, B5 for 15 x 15 package)
The AM335x EMAC interface is an updated version of the module in AM387x. AM335x supports the following new features with respect to AM387x:
- Supports 1588 time-stamping, Industrial Ethernet protocols.
- 1588 Annex D support
- DSCP priority mapping support
- Device Level Ring (DLR) support
- Port changes - added 2 additional clock inputs (and associated IPG DFT signals) to support separate RMII clocks versus RGMII
AM387x includes four McSPI ports, each with four chip select signals.
AM335x includes two McSPI ports, each with two chip select signals.
The SATA controller does not exist on AM335x.
AM387x has 8 General Purpose Timers. All timers are extended to SoC pins.
AM335x has 7 General Purpose Timers. Only 4 timers are extended to SoC pins.
From a module perspective, the timers on both devices are identical.
Both AM387x and AM335x have one watchdog timer.
Both devices have 4 banks of GPIOs, each with 32 dedicated IO pins.
New interfaces in AM335x
The following are new interfaces in the AM335x device that do not exist in AM387x. Any details about these interfaces can be found in the Technical Reference Manual for AM335x.
- PRUSS - Programmable Real-time Unit SubSystem
Pin and package
The AM387x and the AM335x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM387x and the AM335x devices.
|Device||Size (mm)||Pitch (mm)||No. of Pins||Package Designator|
|AM387x||23 x 23 mm||0.80 mm, with VCA||684||Pb-Free BGA (CYE Suffix)|
|AM335x||13 x 13 mm||0.65 mm||298||s-PBGA (ZCE Suffix)|
|15 x 15 mm||0.80 mm, with VCA||324||s-PBGA (ZCZ Suffix)|