Additional Configuration for GPIO120-129 on OMAP35x
From Texas Instruments Embedded Processors Wiki
Background
When using the OMAP35x devices it is very easy to miss a configuration step needed for using gpio_120 - gpio_129. This step is needed regardless of the package type (CBB, CBC, CUS). These pins are unique because they are configurable as 1.8V or 3.0V I/O. Additionally, they include a protection mechanism to isolate the cell as the voltage is ramping.
Configuration
Normally the pin multiplexing is configured by writing to the MODE field of the appropriate CONTROL_PADCONF_X register. For these particular pins (gpio_120 - gpio_129) that is not sufficient. Additionally you need to configure the CONTROL_PBIAS_LITE register. There are several important bit fields that must be configured:
PBIASLITEVMODE0 - sets voltage as 1.8V or 3.0V for gpio_120 - gpio_125
PBIASLITEPWRDNZ0 - buffers the I/O cell for gpio_120 - gpio_125 (needs to be set to 1)
PBIASLITEVMODE1 - sets voltage as 1.8V or 3.0V for gpio_126 - gpio_129
PBIASLITEPWRDNZ1 - buffers the I/O cell for gpio_126 - gpio_129 (needs to be set to 1)
The role of each of these bits is depicted in the following diagram:
If you fail to set the corresponding PBIASLITEPWRDNZ bit then the GPIO will not work properly, i.e. you will not see the correct output on the pad or not read the input from the pad.
Check the Power Rail!
Important: Make sure the vdds_mmc1 and/or vdds_mmc1a supplies are actually being powered (and at the correct voltage) by the power management IC, e.g. the TPS65950. A common issue that people encounter is that the power management IC has not been configured to turn on that rail and so the GPIO does not work!
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Comments
Comments on Additional Configuration for GPIO120-129 on OMAP35x
This is very interesting. If I use just 4 bit MMC1 (120-125) I can then configure 126-129 as GPIO and actually get a 3volt tolerant GPIO on these 4 lines??
--Dvescovi 18:49, 24 February 2010 (CST)