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Analog to Digital Converter Type 0 FAQ for C2000

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This topic is a list of frequently asked questions that users have when using the Analog to Digital Converter of type 0. ADC type 0 is the first ADC module released for the C28x devices. This type is found on the 2810, 2811 and 2812 devices.

Electrical Specifications

Electrical specifications can change between devices, peripheral types and device families. Always refer to the data manual and errata for a particular device for Electrical Specifications.

This page is obsolete and no longer maintained. Refer to C2000 Real-Time Control Peripherals Reference Guide (spru566m) for peripheral type information.

--Lheustess (talk) 15:00, 27 July 2018 (CDT)

Frequently asked questions for ADC Type 0

Q: My converted values are wrong or random. What could be the cause?

Make sure that you have connected ADCLO to AGND

Q: What type of ADC is on the 281x device (Flash, sigma delta... etc?)

The ADC on the 281x is a 4 stage pipeline ADC. At each stage the stored charge in a capacitor is discharged into a set of parallel capacitor banks and the resulting voltage is converted, with each stage generating 3-bits of the 12-bit value. The 3-bit converter is a Flash. It's a good compromise between full Flash converters, which are power hungry but very fast, and SAR (successive approximation) converters, which are slower but more power efficient.

Q: In simultaneous sampling mode is only EVA used as ACSOC ? Is EVB also available or must we use both ?

Simultaneous mode means you will have a pair of channels A0/B0, A1/B1 ...A7/B7 will be sampled at the same instant and converted for results. The pair of channels should be selected before EV trigger for conversion. One Every event trigger (either EVA/EVB or directly from ADC register) two conversion results of the selected channel pair are available. In the continuous conversion, with simultaneous mode after the first trigger, the conversion will be continuous for the selected pair of signals.

Q: I'm having problems configuring the ADC after I reset the ADC using the RESET bit in ADCTRL1 - What can be wrong?

If you use the RESET bit in the ADCTRL1 register, execute 12 NOPs before proceeding with ADC configuration. Please keep in mind that a user is not required to set this bit after powering up. It is only provided so after configuring the ADC registers and using the ADC, the user would have an easy method to get back to the reset condition of the ADC if desired.

Q: What is the maximum ADCCLK?

Max spec is 25MHz. Always refer to the Data Manual for specifications such as this.

Q: If the maximum operation frequency of the ADC (ADCLK) is 25 MHz, how should we get 60ns conversion time when running at only this speed? In the ADC peripherals guide it looks like the ADC is able to output a new value every 2 ADC clock cycles. When running the ADC at 25 MHz, this gives 80ns per result in the sequenced mode. To get 60 ns, the ADC should run at 33 MHz (out of spec?).

To get 60ns, you operate in simultaneous sampling mode. In this mode a pair of matched pins (i.e. ADCINA0 and ADCINB0, or ADCINA5 and ADCINB5, but not ADCINA1 and ADCINB7) is sampled at the same time and fed to the ADC converter in series. The ADC is able to spit out a value in this mode every 1.5 cycles (2 out of 3 cycles). This is how 60ns is attained. The down side is if all you want to do is convert a single channel over and over, you can only get 80ns.

Q: What is the ADC input range on the F2810/F2812? I thought it was 0-3.3V.

The 281x ADC input range is 0-3.0V, not 0-3.3V. Refer to the latest data manual.

Q. What is the function of ADCREFP and ADCREFM? Can my application use these as voltage references?

The ADCREFP and ADCREFM are only output from the device so that the customer can put capacitors on them to keep them as stable as possible. The stability of these signals directly influences the ADC characteristics and we advise against putting any load on them other than the suggested caps. In fact, our specs are only valid if no additional load is applied.

Q: When operating in simultaneous sampling mode, do we still have the benefit of starting the pair of conversion with only one timer just like in cascaded mode via EVA or EVB events?

Yes, Simultaneous sampling mode does not care whether you are in dual or cascaded mode.