Avoiding Double Interrupts with the GPIO Peripheral

From Texas Instruments Embedded Processors Wiki

Contents 1 Summary 2 Example 2.1 Setup resulting in double interrupts 2.2 Setups resulting in one interrupt 3 Diagrams of GPIO Interrupts 4 Avoiding the issue

Summary

When using GPIO interrupts on certain devices it is possible to get interrupted twice due to one interrupt event. This only happens when both the direct interrupt and the bank interrupt are simultaneously enabled. Generally speaking this issue just causes unnecessary interrupt overhead, but depending on how the ISRs are implemented this could potentially cause troubles in the application.

This article is applicable to most newer devices with 64x+ cores in the c6000/Davinci family.

Devices affected (as of May 14, 2009):

• DM355
• DM644x
• DM646x
• C642x
• DM643x

Devices NOT affected (as of May 14, 2009):

• OMAP3530 (different GPIO peripheral)
• C674x (bank interrupts only)
• OMAP-L13x (bank interrupts only)
• C641x (different GPIO peripheral)

This scenario can easily be avoided. For a given bank of 16 interrupts it's recommended to use ONLY direct interrupts or ONLY the bank interrupt, but not both.

Example

Let's take DM355 as an example. Bank0 contains GPIO[15:0]. Let's say we need interrupts from 3 of them, GPIO[2:0].

The ARM Subsystem User's Guide has a table called "AINTC Interrupt Connections" that shows how the peripherals have been connected to the ARM's interrupt controller for that device. In the case of DM355 there are direct interrupts for GPIO0-9 connected to interrupts 44-53 of the controller. The GPIO bank interrupts 0-6 connected to interrupts 54-60.

Setup resulting in double interrupts

Let's say that we use the GPIO0 direct interrupt (#44) to get interrupts that occur on GPIO0, and let's say that we attempt to use bank0 interrupt (#54) to detect GPIO1-2 interrupts. The problem we will encounter is that the GPIO0 interrupt will trigger interrupt #44 and interrupt #54. So in this scenario GPIO1-2 will trigger only #54 but GPIO0 will trigger both #44 and #54.

Setups resulting in one interrupt

Instead we could have used interrupt #44-46 as "direct" interrupts for GPIO0-2. Had we configured things in this way then each GPIO would generate only one interrupt on its corresponding interrupt line.

Alternatively we could have used interrupt #54 to handle all 3 GPIOs and that situation would also avoid two interrupts for a single event.

Diagrams of GPIO Interrupts

Avoiding the issue

Ultimately to avoid this issue you need to make sure that you don't use direct interrupts and the bank interrupt for a given bank of interrupts. That will prevent 2 interrupts from occurring due to a given event.

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