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What is the difference between the TMS320VC5505 and the new TMS320C5505?
The TMS320C5505 (PG 2.0) is based off the TMS320VC5505 (PG 1.4) with silicon bug fixes and feature enhancements.
The differences are summarized in this C5000 Forum post.
What is the pin compatibility of TMS320VC5505 and TMS320C5515?
From a PCB (Print Circuit Board) designer's view point, the TMS320VC5505 and TMS320C5515 are not 100% pin compatible. This application note addresses the PCB design differences between these two devices.
The availability and usage of internal/external LDO are summarized as follows:
- For VC5505, one should use external LDOs for DSP-core and USB
- For C5515, one has the option to use external LDOs or internal LDOs for DSP-core and USB
The following table lists the pin connections for the LDO selections:
|Pin Number||Pin Name||VC5505 (External LDO Only)||C5515 (Internal LDO)||C5515 (External LDO)|
The connection requirements for the reset pin and the DSP_LDOO output pin are different for the VC5505 and C5515. The following table lists the differences.
|Pin Number||Pin Name||VC5505||C5515|
|D6||nRESET||External reset signal is optional||External reset signal is required|
|E10||DSP_LDOO||For proper device operation, this pin must be connected via a 1.0uF decoupling capacitor to VSS||Internal DSP LDO output, it can supply power to the digital core of C5515|
Reminder, for both VC5505 and c5515, pin C8 (CVDDRTC) is the power supply pin of RTC (Real-Time Clock) module, it must be connected to an external power supply.
What are the Hardware and Software requirements to use RTC only mode?
- This document shows hardare and software requirments to use RTC only mode:
What are the differences between the TMS320VC5504/05 and hte TMS320C5504/05/14/15?
These documents provide a summary of the functional differences between the TMS320VC5504/05 and the TMS320C5504/05/14/15 at the device and application levels.
- Device level differences are covered in the document:
- Application level differences are covered in the document:
- The Application Migration Guide references a C5505 PLL Calculator. This calculator is available at:
- CSL (Chip Support Library) differences are covered in the document:
Note: TMS320VC5504/05 and TMX320VC5504/05 (Silicon Revision 1.4) devices will here forth in these documents be referred to as VC5505. The TMS320C5504/05 (Device Revision A, Silicon Revision 2.0) will here forth in these documents be referred to as C5505. The TMS320C5514/15 (Device Revision A, Silicon Revision 2.0) will here forth in these documents be referred to as C5515. When referring to TMS320C5504/05 and TMS320C5514/15 in these documents the term C5505/15 will be used to refer to all four devices.
What are details on using the internal LDOs on the C5515 DSP?
The internal LDOs have a rated maximum current before they shutdown to prevent damage to device circuits. They are as follows:
DSP_LDO provides 1.05V or 1.3V at a maximum current draw of 250mA. This LDO is intneded to supply current to DSP Core (CVDD) only.
USB_LDO provides 1.3V at a maximum current draw of 25mA. This LDO is intended to supply power to the USB_ VDD1P3, USB_VDDA1P3 pins.
ANA_LDO provides 1.3V at a maximum current draw of 4mA. This LDO is intended to supply power to the VDDA_ANA and VDDA_PLL pins.
The LDOs in the C5515 should NOT be used to power C5505 I/O power domains.
This maximum current draw needs to understand that a device may peak current much higher than the nominal current draw. This could happen if all peripherals and core are heavily processing data. Thus, we do not recommend connecting the LDO outputs to the external devices since the DSP can consume all the current the LDOs can produce.
If you connect multiple regulators to the same supply, the regulators may not exactly match their regulated voltages. Thus, some regulators might consume large current to raise the voltage to the expected standard, while others might lower their current consumption because their voltage is too high. Thus, we do not recommend connecting more than one regulator to a supply rail.
Reference: E2E Forum Post
What are the software requirements for my code to run standalone on the C5515 eZdsp?
Make sure your project (.c file) explicitly configures the PLL of the C5515 DSP (this is usually done with the GEL file, but the GEL file does not get replicated in the COFF object file output of the build (.out file)
Code like this:
#define CONFIG_MSW *(ioport volatile unsigned *)0x1C1F // Clock Configuration MSW #define PLL_CNTL1 *(ioport volatile unsigned *)0x1C20 // PLL Control Register #1 #define PLL_CNTL2 *(ioport volatile unsigned *)0x1C21 // PLL Control Register #2 #define PLL_CNTL3 *(ioport volatile unsigned *)0x1C22 // PLL Control Register #3 #define PLL_CNTL4 *(ioport volatile unsigned *)0x1C23 // PLL Control Register #4
If you have a custom entry point then make sure you add the following section at the beginning to configure the PLL. In case you are using the standard flow, include the following lines in the main:
int delay = 132; //Delay 4ms while SYSCLK = 32768 CONFIG_MSW = 0x0; PLL_CNTL1 = 0x8BE8; //Config C5515 (PG2.0) to 100MHZ PLL_CNTL2 = 0x8000; //Config C5515 (PG2.0) to 100MHZ PLL_CNTL3 = 0x0806; //Config C5515 (PG2.0) to 100MHZ PLL_CNTL4 = 0x0000; //Config C5515 (PG2.0) to 100MHZ while ( delay-- > 0); CONFIG_MSW = 0x1;
How do I burn my code into the NOR flash of C5515 eZdsp?
Please click here for the procedure to burn the NOR flash on the C5515 eZdsp.
Which version of the Code Generation Tools should I use with C55XCSL-LOWPOWER for the VC5505?
The documentation states that CGT v4.3.3 and above should be used. However, a bug (cite please) was introduced in v4.3.3 and carried through v4.3.5. A fix has been implemented and released in CGT v4.3.6, so this is the recommended version for VC5504/05, C5504/05 and C5514/15 DSPs. The new release is now available through CCS3.x Update Advisor.
What version of DSP/BIOS supports the TMS320C5515 device?
Support for C5515 (and evm5515) was added in BIOS 5.41.03 (Feb 10, 2010). You can get it here
There's a separate installer for CCSv3 and CCSv4.
If you are using CCSv3, the CCSv3 installation contains examples for the evm5515.
If you are using CCSv4, you will also need to download and install XDCTools 3.16.03.36 which you can get here
You can update the evm5505 examples' .tcf files to change 'loadPlatform('evm5505')' to 'loadPlatform('evm5515').
Are there CPU Advisories for the new v3.3 CPU used in the TMS320c5504/05/14/15 devices?
The CPU Programmer's Reference Supplement contains CPU advisories for the v2.x CPU used in the TMS320VC5501/02/03/06/07/09A/10A devices. The newer CPU is not covered. Advisories for the v3.3 CPU are shown in this document: Media:C55x Rev3 CPU Advisories.pdf. All previous advisories were corrected in the design of the v3.3 CPU.
Description of USB FIFO addresses in SPRUGH9, pg 107 is not clear. Can you clarify?
The USB Endpoint FIFO space is a sepcial RAM inside the USB module. It is not related to the DARAM or SARAM in the C5515/05. It is 4KB in total. The endpoint 0 is always start at address 0 and it is is always 64 byte in size. Both IN/OUT of EP0 share this area. The Endpoint 1-4 must allocate their own FIFO spaces for IN and OUT separately. The size of the FIFO space for each EP (IN and OUT) is depending on the usage, but the total FIFO space should be less or equal then 4KB. The FIFO address is in 8-byte unit. The FIFO size is 2^(m+3) where m is the FIFO size in the register. Here is an example for EP0 (64 byte), EP1 IN (64 byte), EP1 OUT (64 byte) and EP2 IN (512 byte):
EP0_SIZE = 3; // EP0 IN FIFO size 2^(3+3) = 64, it is default on reset
EP0_FIFO_ADDR = 0; // EP0 IN FIFO start at 0 byte, it is default on reset
EP1_IN_SIZE = 3; // EP1 IN FIFO size 2^(3+3) = 64
EP1_IN_FIFO_ADDR = 8; // EP1 IN FIFO start at 64 byte (8x8)
EP1_OUT_SIZE = 3; // EP1 IN FIFO size 2^(3+3) = 64
EP1_OUT_FIFO_ADDR = 16; // EP1 OUT FIFO start at 128 byte (16x8)
EP2_IN_SIZE = 6; // EP2 IN FIFO size 2^(6+3) = 512
EP2_IN_FIFO_ADDR = 24; // EP2 IN FIFO start at 192 byte (24x8)
The total FIFO space used so far is 64 (EP0) + 64 (EP1 IN) + 64 (EP1 OUT) + 512 (EP2 IN) = 704 byte
The more EPs used the more FIFO space is needed. The FIFO size for each EP is also regulated by the USB spec. The maximum FIFO size for each EP:
High Speed ISO: 1024
High Speed Bulk: 512
FullSpeed Bulk: 64
The correct FIFO allocation method is implemented in the CSL 2.10
Can I use a contact piezo film transducer with Digital Stethoscope MDK?
The analog front end has circuit to support this transducer type, but the Digital Stethoscope application does not implement support for this HW. The Digital Stethoscope application only supports a condenser microphone as documented in the Digital Stethoscope Application Note.
How to format a partitioned MMC/SD card for MMC/SD boot?
Use this free format tool to format a partitioned card. C5515/15/05/04 can only boot from partitioned card. http://download.cnet.com/HP-USB-Disk-Storage-Format-Tool/3000-2094_4-10974082.html Refer to C5515 Boot-Image Programmer for encrypted boot image details.
CCS returns this error: "This project was created for a device-variant that is not currently recognized: TMS320C55XX.TMS320VC5515. Please install the device-variant descriptor, or migrate the project to one of the supported device-variants"
Some projects reference a "TMS320VC5515" device name which does not match the actual part number (no 'V'): TMS320C5515. CCS was fixed to reflect the correct C5515 device name, but projects with the VC5515 device require device name change to import into CCS. Follow these steps:
- Close the project and delete it from CCS (do not delete contents)
- Edit .cdtbuild and .ccsproject files in the project directory
- Find and replace “TMS320VC5515” with “TMS320C5515”
- Save modified files
- Import the project again
- Rebuild the project