C64x+ Cycle Accurate Simulator

From Texas Instruments Embedded Processors Wiki

Contents 1 C64x+ Cycle Accurate Simulator 1.1 Components Model 1.1.1 Internal Memory Configuration 1.1.2 Timer Model 1.2 Simulator Configurable Options 1.2.1 Simulator Configurable Options in CCSv4 1.2.2 Simulator Configurable Options in CCSv3.3 1.2.2.1 Internal Memory Configuration 1.2.2.2 Timer Model configuration 1.2.2.3 Runtime Memory Limit 1.3 Running Applications

C64x+ Cycle Accurate Simulator

This simulator is a C64x+ CPU only simulator and it's also cycle accurate simulator. This is generic C64x+ simulator with cache system modeled & comes with a predefined configuration/memory map; Mainly used in algorithm development where the development is CPU centric.

Components Model

Components modeled in C64x+ Cycle Accurate Simulator.

• C64x+ core, cache system , 2 timer models
• Memory with single cycle latency.
• Interrupts 4 -127 supported on the boundary

Internal Memory Configuration

C64x+ Cycle Accurate Simulator models all the internal memory along with cache configurations. Internal memories are Data Memory Controller (DMC), Program Memory Controller (PMC) & Unified Memory Controller (UMC). Memory region falling outside the CPU are part of External Memory Controller (EMC) and they are program accessible with single cycle latency.

Timer Model

The C6000™ DSP device has 32-bit general-purpose timers that can be used to: Time events, Count events, Generate pulses, Interrupt the CPU and Send synchronization events to the DMA.

Timer Memory Map

• Timer0: Memory map - 0x02940000 - 0x0294003F

• Timer1: Memory map - 0x02980000 - 0x0298003F

Interrupt connection for Timer models

• CPU pin 67 (Intsel_in_pin_67) to Timer_0 Event TIN12 (TIMER64_0_cpu_int_12)

• CPU pin 68 (Intsel_in_pin_68) to Timer_0 Event TIN34 (TIMER64_0_cpu_int_34)

• CPU pin 69 (Intsel_in_pin_69) to Timer_1 Event TIN12 (TIMER64_1_cpu_int_12)

CPU pin 69 (Intsel_in_pin_70) to Timer_1 Event TIN34 (TIMER64_1_cpu_int_34)

Simulator Configurable Options

C64x+ Cycle Accurate Simulator can be configured to match other C64x+ device by configuring the internal memory & timer. Follow the step to configure internal memory to different cache & SRAM sizes & Timer model to different memory map & interrupt connection.

Simulator Configurable Options in CCSv4

• Create a target configuration and select C64x+ Megamodule Cycle Accurate Simulator

• Goto Advanced Setup by clicking on the Advanced tab or Target Configuration link. Summary will give information on the cache size & Timer configuration on the selected device.

• Select the appropriate Device memory map i.e the intended target device. If your Device is not listed select the closest one.

• Save the configuration & bring up the simulator. Note: Cache configuration & timer configuration are internally done based on the selection.

Simulator Configurable Options in CCSv3.3

Simulator is configured via simulator configuration file in CCSv3.3. Please follow the step given below.

Internal Memory Configuration

Configure DMC

• Step 1: Go to CCS installation, and drivers folder. Open “simc64plus.cfg” configuration files. (Create a backup of file as precautions)

• Step 2: Search for “Module DMC” & go to the locations.

Ex:
   MODULE DMC;
       CACHE_SIZE         0x0000;
       MEMORY_SIZE        0x100000;
       SRAM_START_ADDRESS 0x00F00000;
   END DMC; 

SRAM_START_ADDRESS – Start address of DMC
MEMORY_SIZE – Total size of DMC memory. Ex: 0x100000 = 1 Mbytes, 0x8000 = 32 Kbytes.
CACHE_SIZE – Cache memory size in DMC memory. Cache size can’t be greater than total memory size.

Note: SRAM size is the difference total memory size and cache size. 

• Step 3: Modify the SRAM_START_ADDRESS, MEMORY_SIZE & CACHE_SIZE accordingly to desired device memory configuration.

Ex: For C6455 simulator - DMC
   MODULE DMC;
       CACHE_SIZE         0x8000;
       MEMORY_SIZE        0x8000;
       SRAM_START_ADDRESS 0x00F00000;
   END DMC;

Configure PMC

• Step 1: Go to CCS installation, and drivers folder. Open “simc64plus.cfg” configuration files. (Create a backup of file as precautions)

• Step 2: Search for “Module PMC” & go to the locations.

Ex:
   MODULE PMC;
       CACHE_SIZE         0x0000;
       MEMORY_SIZE        0x100000;
       SRAM_START_ADDRESS 0x00E00000;
   END PMC; 

SRAM_START_ADDRESS – Start address of PMC
MEMORY_SIZE – Total size of PMC memory. Ex: 0x100000 = 1 Mbytes, 0x8000 = 32 Kbytes.
CACHE_SIZE – Cache memory size in PMC memory. Cache size can’t be greater than total memory size.

Note: SRAM size is the difference total memory size and cache size. 

• Step 3: Modify the SRAM_START_ADDRESS, MEMORY_SIZE & CACHE_SIZE accordingly to desired device memory configuration.

Ex: For C6455 simulator - PMC
   MODULE PMC;
       CACHE_SIZE         0x8000;
       MEMORY_SIZE        0x8000;
       SRAM_START_ADDRESS 0x00E00000;
   END PMC;

Configure UMC

• Step 1: Go to CCS installation, and drivers folder. Open “simc64plus.cfg” configuration files. (Create a backup of file as precautions)

• Step 2: Search for “Module UMC” & go to the locations.

Ex:
   MODULE UMC;
       CACHE_SIZE         0x00000;
       MEMORY_SIZE        0xE00000;
       SRAM_START_ADDRESS 0x00000000;
       RAM_WAIT_STATES    1;
   END UMC;

   SRAM_START_ADDRESS – Start address of UMC
   MEMORY_SIZE – Total size of UMC memory. Ex: 0x100000 = 1 Mbytes, 0x8000 = 32 Kbytes.
   CACHE_SIZE – Cache memory size in UMC memory. Cache size can’t be greater than total memory size.
   RAM_WAIT_STATES –  No. of excess cycle taken for read/write access.

   Note: SRAM size is the difference total memory size and cache size. 

• Step 3: Modify the SRAM_START_ADDRESS, MEMORY_SIZE, CACHE_SIZE & RAM_WAIT_STATES accordingly to desired device memory configuration.

Ex: For C6455 simulator - UMC
   MODULE UMC;
       CACHE_SIZE         0x00000;
       MEMORY_SIZE        0x200000;
       SRAM_START_ADDRESS 0x00800000;
       RAM_WAIT_STATES    1;
   END UMC;

Timer Model configuration

• Step 1: Go to CCS installation, and drivers folder. Open "simc64plus.cfg" configuration files. (Create a backup of file as precautions)

• Step 2: Search for "TIMER0_mif" or "TIMER1_mif", and go the locations.

Ex: 
   CONNECT23 C64xplus.MM.EMCCtrlecfg_mem_map, TIMER64_0_mif, 0x02940000, 0x0294003F, -0x02940000;
   CONNECT24 C64xplus.MM.EMCCtrlecfg_mem_map, TIMER64_1_mif, 0x02980000, 0x0298003F, -0x02980000;

   Note: Last 3 hex values represent the start address, end address & offset.

• Step 3: Change the start address, end address & offset for TIMER0 & TIMER1 accordingly.

Ex: 
   CONNECT1 C64xplus_mem_map, TIMER0_mif, start_address, end_address, -start_address;

• Step 4: Mapping Timer TIN12 & TIN34 interrupt. Search for “TIMER64_0_cpu_int_12” & “TIMER64_0_cpu_int_34”.

Ex:
   CONNECT25 C64xplus.MM.Intsel_in_pin_67, TIMER64_0_cpu_int_12;
   CONNECT26 C64xplus.MM.Intsel_in_pin_68, TIMER64_0_cpu_int_34;

• Step 5: Change the CPU interrupt to the desired pin, by changing the interrupt number.

Ex:
   CONNECT25 C64xplus.MM.Intsel_in_pin_4, TIMER64_0_cpu_int_12;
   CONNECT26 C64xplus.MM.Intsel_in_pin_5, TIMER64_0_cpu_int_34;

   Note: C64x+ Cycle Accurate simulator support interrupt 4-15 only.

• Step 6: Repeat the Step 4 & 5 for Timer1 - “TIMER64_1_cpu_int_12” & “TIMER64_1_cpu_int_34”

• Step 7: Save the configuration and bring up the simulator.

Runtime Memory Limit

Simulator support 64MB as memory limit for application, beyond that it gives an error. To increase the runtime memory limit add the following line in simulator configuration file inside Module C64xplus;

MODULE C64xplus;

      MEM_USAGE_LIMIT 100; // Supposing you want to change to 100 MB
      ....

END C64xplus;

Running Applications

All BIOS application will run on simulator after selecting the appropriate devices which intern configure the timer memory map & interrupt configurations.

Note: In CCSv3.3 while running BIOS application check whether the simulator timer memory map & interrupt configuration matches the intended device.

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