C6747 Audio Example cache configuration
From Texas Instruments Embedded Processors Wiki
Performance improvement
For some examples that come in the C6747 software, you can get an improvement in performance specially if you have important code/data in external memory. To install the software please follow the Getting Started Guide for C6747.
Understanding Cache Configuration
To understand the MAR bits and when it is good to use the cache, please see:
- C6747 datasheet page 15 (Table 3-2. C674x Cache Registers).
Example of changing cache configuration
If you open the audio example at:
C:\Program Files\Texas Instruments\pspdrivers_01_20_00\packages\ti\pspiom\examples\evm6747\audio\build
You can open the DSP/BIOS Configuration file (audioSample.tcf) and change the cache configurations for a better performance. You simply go to System, right-click on Global Settings, and select Properties. Then you go to the 64PLUS tab and you'll see this dialog box. Change the 64P L2CFG Mode from 0K to 32K (or more), and configure the MAR bits to allow L3 and SDRAM (EMIFB) to be cacheable:
A new memory section called CACHE_L2 will appear:
All you need to do it to adjust the IRAM section size. The amount of L2 IRAM memory used for cache should be taken from the IRAM length. So, for 32K of L2 Cache, the len field goes from 0x40000 to 0x38000.
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