C6747 Watchdog example
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In construction.
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What is it?
This is an example on how to enable and use the watchdog timer for the C6747 device.
Prerequisites
CCSv3 with at least SR12 - you can get SR updates at Update Advisor.
Install the C6747 software according to the Getting Started Guide for C6747.
This example was tested with the C6747 EVM from Spectrum Digital.
Installing the Software
Download the timer_watchdog.zip file from this link in the TI forum.
You can unzip this project at (so you do not have build errors):
C:\Program Files\Texas Instruments\pspdrivers_xx_xx_xx\packages\ti\pspiom\cslr\evm6747\examples
or equivalent if you did not install the software in the default path.
Building the application
- Open CCS, and connect to the C6747 board.
- Open the project ...\build\Timer_example.pjt
- Click Project-> Build
Running the application
To Run the application, simply click on Debug->Run in CCS.
There is a PRD (pet_watchdog) that will prevent the watchdog to reset the processor. So if you run the project as is the watchdog will not reset the DSP.
If you want to see the watchdog in action, you can comment the contents of the pet_watchdog() function:
#pragma FUNC_EXT_CALLED(pet_watchdog); // for -o3 in release mode void pet_watchdog(){ // CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD1); // Go to Service state // CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD2); // Return to Active state }
Build and run the application for a little while. The watchdog will force a hardware reset. If you try to halt the processor you will see that the CCS needs to disconnect because the hardware reset occured.
This will only work after you turn on your board for the first time for emulation boot mode. If you want to test it again you need to turn off CCS, power cycle the board and turn on CCS again. This is because the watchdog itself needs a hardware reset to be re-enabled after it was serviced.
After the hardware reset forced by the watchdog, the DSP will reboot. If the boot mode is emulation and/or your board is connected to CCS, then it will not reload the code automatically because you need to reconnect to CCS and load. If, for example, your code were in a FLASH memory (and equivalent boot mode), then after a hardware reset it would be reloaded.
Usage Notes
Timer used by DSP/BIOS
According to the C6747 datasheet page 160, section 6.23, only Timer1 can be used as watchdog. Timer0 can not be used as watchdog.
DSP/BIOS uses one of the timers of the DSP for the CLK manager. It is possible to select the specific timer to be used at the DSP/BIOS configuration file. To do that, open the DSP/BIOS configuration file (.tcf), expand Scheduling. Right click on CLK - Clock Manager and select Properties. See Timer Selection:
For this watchdog example, it is necessary to select Timer 0 for DSP/BIOS to make sure that it does not interfere with the watchdog timer (Timer 1).
Debugging
Compilation failure
If you get the compilation failure like the one below:
------------------------- Timer_example.pjt - Debug ------------------------- [watchdog.c] "C:\Program Files\Texas Instruments\C6000 Code Generation Tools 6.1.13\bin\cl6x" -g - fr"../obj/Debug" -i"../../../../../../../" -d"_DEBUG" -mo -ml3 -mv6740 -@"../build/Debug.lkf" "watchdog.c" "watchdog.c", line 40: fatal error: could not open source file "ti/pspiom/cslr/soc_C6747.h" 1 fatal error detected in the compilation of "watchdog.c". Compilation terminated. >> Compilation failure Build Complete, 1 Errors, 0 Warnings, 0 Remarks.
It means that you probably did not follow the suggestion in the Installing the Software section to put the example project at (so you do not have build errors):
C:\Program Files\Texas Instruments\pspdrivers_xx_xx_xx\packages\ti\pspiom\cslr\evm6747\examples
If you do not want to put the project there, you can simply add the path to the soc_C6747.h in the build options. Right click on the project, select Build Option..., choose the Compiler tab, Preprocessor Category. Put the relative path to the file (C:\Program Files\Texas Instruments\pspdrivers_01_30_00_06\packages for example) in the Include Search Path (): field:
Related Links
Getting Started Guide for C6747
TMS320C674x/OMAP-L1x Processor 64-Bit Timer Plus User's Guide
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Comments
Comments on C6747 Watchdog example
I have run into what appears to be a discrepancy in some reference material. I am trying to enable the internal watchdog on the C6747. According to SPRUFM5C (12/2010), the default time base for the 64-bit Timer plus module is the “Internal Clock”. According to the first sentence of section 2.1.2.1, the “internal clock source to the timer is generated by the PLL controller”.
Our board is driven by an oscillator source at 24 MHz. Using the oscillator, the PLL controller provides a system frequency output of 300 MHz. From observation, it appears the timer counter registers when running in 64-bit WDT are being clocked at 24 MHz. Because of the documentation, I expected this input to the timer to be at 300 MHz.
Can you have someone confirm or deny this finding? Is the timer "internal clock" source the oscillator or the PLL output?
--Mjmanthey 12:04, 4 January 2011 (CST)