CC3000 Serial Port Interface (SPI)

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CC3000 Serial Port Interface


The SPI is based on the five-line, master/slave communication model as shown in the following figure:
Masterslave communication model.jpg

The lines are described as follows:

I/O Description
CLCK(1) Clock (~0 to 16 MHz) from host to slave
nCS(2) nCS (active low) signal from host to slave
MOSI Data from host to slave
IRQ(3) Interrupt from slave to host
MISO Data from slave to host

  • (1)CLCK provides a clock to the SPI interface on the CC3000 device.
  • (2)nCS selects a CC3000 device, indicating that a master wants to communicate to the CC3000 device. MISO is not set to Hi-Z when nCS is deasserted.
  • (3)IRQ is a dual-purpose slave to the master direction line: in SPI IDLE state while no data transfer is active, driving IRQ low indicates to the master that the CC3000 device has data to pass to it; driving IRQ low following nCS deassertion indicates that the CC3000 device is ready to receive data. All behaviors are explained in detail in the following sections.

Protocol Description

The SPI protocol is used to communicate with the CC3000 device from the host MCU that is acting as the SPI master while the CC3000 device is the SPI slave. The protocol is an extension of the existing standard SPI. The endianness on transport is assumed to be most-significant bit (MSB) first.

The clock and phase settings for the SPI are configured such that the data is sampled on the falling edge of the clock cycle. Note that different MCU may use different naming conventions in order to configure SPI clock phase and polarity, For example, MSP430 uses UCCKPL and UCCKPH for clock polarity and phase respectively. Both are set to 0, indicating that the data is sampled on the falling edge of the clock cycle. The more generic convention is CPOL and CPHA, however, in order to configure sampling on the falling edge of the clock cycle, CPHA is set to 1.

All data sent or received over the SPI interface must be 16-bit aligned. A padding byte is added where required. Each packet passing on the SPI bus consists of a 5-byte SPI header followed by user data and optionally by a padding byte so that the whole length is 16-bit aligned, as shown in the next Figure.
SPI header.jpg

The first byte of the header is an operation opcode (READ or WRITE) followed by two bytes that indicate the size of the payload length (including the alignment byte). Two busy bytes then follow to conclude the header.

The data payload directly follows the last byte of the header. The padding byte is added when the length of the payload part of the packet is even.

Master Write Transaction

There is a slight difference between the first master write transaction after power up and the rest of the write transactions. The difference follows from the internal CC3000 implementation of SPI.

Master Write Transaction Header
The header precedes each data packet. The structure of the header (see figure below) is independent of whether or not it is a first write transaction.
Master Write Transaction Header.jpg

The first byte of the header is the write opcode followed by two bytes that indicate the size of the payload length (including the alignment byte). Two busy bytes then follow to conclude the header.

The data payload directly follows the last byte of the header. The following summarizes the header structure:

Write = Opcode for write is 0x01
M<sub>MSB</sub>, M<sub>LSB</sub> = 16-bit data payload length (including alignment byte)
Busy = Busy byte (0x00)
Busy = Busy byte (0x00)
First Host Write Operation

The first write transaction to occur after release of the shutdown has slightly different timing than the others.

The normal Master SPI write sequence is nCS low, followed by IRQ low (CC3000 host), indicating that the CC3000 core device is ready to accept data. However, after power up the sequence is slightly different, as shown in the following Figure:
CC3000 Master SPI Write Sequence After Power Up.png
The following is a sequence of operations:
  1. The master detects the IRQ line low: in this case the detection of IRQ low does not indicate the intention of the CC3000 device to communicate with the master but rather CC3000 readiness after power up.
  2. The master asserts nCS.
  3. The master introduces a delay of at least 50 μs before starting actual transmission of data.
  4. The master transmits the first 4 bytes of the SPI header.
  5. The master introduces a delay of at least an additional 50 μs.
  6. The master transmits the rest of the packet.
Generic Host Write Operation
  1. The master asserts nCS (that is, drives the signal low) and waits for IRQ assertion.
  2. The CC3000 device asserts IRQ when ready to receive the data.
  3. The master starts the write transaction. The write transaction consists of a 5-byte header followed by the payload and a padding byte (if required: remember, the total packet length must be 16-bit aligned)
  4. After the last byte of data, the nCS is deasserted by the master.
  5. The CC3000 device deasserts the IRQ line.
The following figure shows a master write transaction.
CC3000 Master Write Transaction.png

Master Read Transaction

The master read transaction is initiated by the CC3000 device by asserting (that is, driving low) an IRQ line while the bus is in IDLE state. If a master detects an IRQ assertion while in the process of initialization of the master write transaction, it is up to the master to resolve the order of read and write operations. If the master continues with the master write transaction, the deasserted IRQ can be treated as a deassertion that is required as a response to nCS. The following is a sequence:

  1. The IRQ line is asserted by the CC3000 device.
  2. The master asserts the nCS line.
  3. The master transmits the following 3 bytes: read opcode followed by two busy bytes.
  4. The CC3000 sends back the following data: the first two bytes indicate the payload length and the data payload bytes follow, immediately after.
  5. At the end of read transaction, the master drives nCS inactive.
  6. The CC3000 device deasserts an IRQ line.

The following figure shows the master read transaction process.

CC3000 Master Read Transactoin v2.png

Master Read Transaction Header

The following summarizes the master read transaction header structure:

Read = Opcode for write is 0x03
SMSB, SLSB = 16-bit data payload length (including alignment byte)
Busy = Busy byte (0x00)

Example Implementation of SPI

The following two sections present two example implementations of the CC3000 SPI interface in terms of state-machines. The first implementation is based on the MSP430, which does not use DMA during read/write operations (also called the busy waiting approach) and thus the state-machine is much easier but more MCU tight. The second implementation is based on the LM3S9B96 Stellaris, which uses DMA for data transfer to or from the SPI.

Busy Waiting SPI Implementation

Write operation
The following figure shows the write operation flow.
CC3000 Write Operation Flow.png

In this implementation the write operation is performed from the context of the interrupt on the IRQ line.

Read operation
The following figure shows the read operation flow.
CC3000 Read operation flow.png

In this implementation the interrupt on the IRQ line is enabled after processing the received data.

DMA based SPI implementation

Direct memory access (DMA)-based operation has more states to handle compared to nonDMA-based operation. Moreover, it is a more asynchronous-like implementation based on interrupts from the DMA module.

Write operation

The following two figures show SPI write implementation for the DMA-based SPI.

A limitation of the LM3S9B96 data buffer prevents more than 1024 bytes from being copied in one transaction of the DMA from RAM to the SPI FIFO; thus, two DMA transactions are required.
CC3000 DMA-Based Write Operation Flow (1 of 3).png
After the nCS is activated, the host continues operating in main loop until IRQ interrupt detected.
CC3000 DMA-based write operation flow (2 of 3).png

After triggering DMA in the context of the IRQ interrupt handler to write the whole packet or part of the packet as described, the context returns to the main loop, while the SPI portion waits for the DMA-complete interrupt (see figure below).
CC3000 DMA-based write operation flow (3 of 3).png

Read operation
The following figure shows an SPI read operation of the DMA-based implementation of the SPI interface. The read operation is triggered by an IRQ line activation and reception of the interrupt on the IRQ line.
Interrupt on IRQ low.jpg

After triggering a DMA to read first 10 bytes, the control returns back to the non-interrupt context, waiting for DMA complete interrupt.

DMA complete.jpg

CC3000 Init Operation

CC3000 has a unique command sequence in order to initialize.

Host sends to CC3000 device the commands over SPI and waits for ‘command complete’ for each command from CC3000.

 1. The first command the host should send CC3000 is HCI_CMND_SIMPLE_LINK_START with one argument which specifies if patches are available at host or not.

 2. As a response, CC3000 will return ‘command complete’ for this event which specifies the same opcode of the command.

 3. The following command the host will send CC3000 is HCI_CMND_READ_BUFFER_SIZE with no arguments.

 4. As a response, CC3000 will return ‘command complete’ for this event which specifies the same opcode of the command.

At this stage, CC3000 device is awake and ready to receive any command, or send any API in the host driver.

1. Host ->> CC3000  -   HCI_CMND_SIMPLE_LINK_START

Host sends CC3000 over SPI the first command: HCI_CMND_SIMPLE_LINK_START (command opcode 0x4000)
Data: 0x01 0x00 0x05 0x00, minimum 50 ­µs pause, 0x00 0x01 0x00 0x40 0x01 0x00


First 4 bytes:


The remaining 6 bytes:


2. CC3000 ->> Host - HCI_EVNT_SIMPLE_LINK_START command complete

CC3000 sends Host over SPI the command complete event for first command received: HCI_EVNT_SIMPLE_LINK_START (event opcode 0x4000 - the same as for command HCI_CMND_SIMPLE_LINK_START). Note that the Host MUST output 0x03 as the first byte or else the CC3000 will not send the remaining bytes.

Data: 0x02 0x00 0x00 0x00 0x05 0x04 0x00 0x40 0x01 0x00



Host sends CC3000 over SPI: HCI_CMND_READ_BUFFER_SIZE (command opcode 0x400b)

Data: 0x01 0x00 0x05 0x00 0x00 0x01 0x0b 0x40 0x00 0x00



4. CC3000 ->> Host - HCI_EVNT_READ_BUFFER_SIZE command complete

CC3000 sends Host over SPI the event for HCI_EVNT_READ_BUFFER_SIZE notifying the command was completed successfully. The arguments of the message carry the queried data about the buffers.

Data: 0x02 0x00 0x00 0x00 0x09 0x04 0x0b 0x40 0x04 0x00 0x06 0xdc 0x05 0x00 (command complete for opcode 0x400b = HCI_CMND_READ_BUFFER_SIZE)

  • Number of buffers returned from CC3000: 0x06
  • The length of buffers returned from CC3000: 0x05dc = 1500

The last byte of the message (0x00) is optional padding byte in order to achieve 16-bit aligned SPI packet.


The reason behind the short pause between 10th and 11th message byte in the analyzer capture above is due to host driver implementation of SDK. After reading in the first 10 bytes of the message, it processes the SPI header to figure out how many additional bytes need to be clocked out from CC3000. If SPI payload length given in SPI header is greater than 5, then it continues reading from CC3000 the remaining bytes.

Related Pages

The following pages, use the SPI's page as a reference

  1. Host Programming Guide
  2. Host Driver Porting Guide

Additional References: Host Controller Interface

  1. Host Controller Interface

This page addresses the logical communication protocol between the CC3000 wireless module and SPI host. The content of this page applies to CC3000 Service Pack v1.12 (CC3000 firmware version 1.26).