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Cache Visualization

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This topic gives technical details on usage of how to visualize cache effects with both the Simulator and XDS560 Trace.

Download the presentation at SystemLevelCacheVisualization08.pdf

Topics

  • Cache Effect Analysis with XDS560 Trace
  • Cache Analysis with Simulation Tools
  • System Level Cache Optimization

Note you can use the Advanced Event Triggering to collect basic cache information in counters built onto selected devices. See: Unified Breakpoint Manager

Q: CacheTune General Adivce

CacheTune is a new tool that helps the developer attain high levels of cache efficiency by addressing the issues in cache visualization, analysis and optimization. It graphically visualizes program and data cache accesses over time, which enables quick and effective reorganization of non-optimal cache utilization. The tool also provides proactive advice in guiding the developer to analyze the memory accesses patterns and tune the cache memory subsystem to meet performance goals.
You may manually open the CacheTune adivce window by selecting the menu item under CCS-> Profile ->Tuning->CacheTune.
This application reports SPRA001 introduces the CacheTune tool development flow to tune your application for a high level of cache efficiency.
For more information on CacheTune, you can also refer to CCS contextual help
 

Q: Is cache coherence automatically maintained between external memory and L2 cache?

When external memory caching is enabled, the cache controller does not maintain coherence between the external memory and L2/L1 cache. It is the responsibility of the user to maintain this coherence. CPU accesses will see the contents of cacheable external memory through the L1D and L2 cache. The values held in cache may not match what is held in external memory. Since the cache controller does not maintain coherence, the CPU may not see the same data as a peripheral or DMA would if it accessed the same address in external memory. If and when required, coherence between CPU and peripheral accesses to external memory can be achieved by manually issuing cache coherence commands to the cache controller.

This application report SPRU656 explains the fundamentals of memory caches and describes how to efficiently utilize the TMS320C6000 DSP two-level cache-based memory architecture. It shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency.