Category:Control Law Accelerator Type0

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Introduction

The C28x Control Law Accelerator (CLA) is an independent, fully-programmable, 32-bit floating-point math processor that brings concurrent control-loop exceuction to the C28x family. The low interrupt-latency of the CLA allows it to read ADC samples "just-in-time". This significantly reduces the ADC sample to output delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is free to perform other system tasks such as communications and diagnostics.

Control Law Accelerator Type 0

The Control Law Accelerator module described in these pages is a Type 0 CLA. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a CLA module of the same type, to determine the differences between the types, and for a list of device-specific differences within a type. This document describes the architecture, pipeline, instruction set, and interrupts of the C28x Control Law Accelerator.

Pages in category "Control Law Accelerator Type0"

The following 3 pages are in this category, out of 3 total.