"For FRAM devices running at higher than 8MHz, FRAM waitstate needs to be configured accordingly."
On the MSP430 devices with FRAM, the FRAM operating frequency is limited to 8MHz. When the device operates at higher frequency (MCLK>8MHz), FRAM should be configured to allow for sufficient delays between FRAM memory accesses. This can be achieved by inserting the appropriate amount of waitstates between FRAM accesses based on the operating frequency.
If the FRAM waitstate is not properly configured, FRAM accesses
when device is running at higher than 8MHz can be corrupted and
resulting in runtime failure.
The FRAM waitstate configuration code cannot be detected in the
project.
Note: keep in mind that this compiler check does not verify
whether the sufficient amount of waitstates is configured.
If the device is not running at higher than 8MHz, no remedy is necessary. Otherwise, prior to having the device run at higher than 8MHz, add the following lines of code to add FRAM waitstate configuration:
// Configure one FRAM waitstate as required by the device datasheet for MCLK // operation beyond 8MHz _before_ configuring the clock system. FRCTL0 = FRCTLPW | NACCESS_1; // Change the NACCESS_x value to add the right amount of waitstates
Refer to FRAM device code examples from CCS - TI Resource Explorer or as downloadable packages at https://www.ti.com/lsds/ti/microcontroller/16-bit_msp430/tools_software.page#code
Refer to the MSP430 Family User's Guides for FRAM devices for more details.
For more questions/answers, Go to
MSP430's e2e online forum!
If you are posting on the forums in relation to this rule, try using the tags "DiagMessage_10421" and "FRAM_WaitState"
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