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Introduction to Concerto Dual-Core Boot

This article explains how to setup the boot process for Concerto F28M35x. It also includes frequently asked questions with regards to Concerto dual-core boot.

Documentation

The boot process for these devices is described in more detail in the Boot ROM section of the Technical Reference Manual (TRM):

• F28M35x Technical Reference Manual (TRM) SPRUH22

Examples

It is recommended that you begin with the dual-core blinky example in controlSUITE. This example can be found in the following directory:

C:\TI\controlSUITE\device_support\f28m35x\<version>\F28M35x_examples_Dual\blinky

Where <version> is v110 or later.

Debugging Flash Dual-Core Boot

In order to debug any issues running from flash without a debugger connected it is recommended to first enable dual boot with a debugger connected. This will give you visibility to the boot process and help pin-point any issues.

Check the Boot Mode Pins

• Make sure to set boot mode pins to boot-to-flash configuration before you start the M3 application.

Load the Application

1. Launch the F28M35x debugger connection. Connect to the M3 and to the C28x.
2. Select the M3 application
   1. Make sure there is an inter-processor command (IPC) for the M3 to tell the C28x to initialize RAM and to boot to FLASH.
      • IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);
      • This command will tell the C28x to initialize the RAM and then boot to Flash
        
        
        

        IPC command to tell the C28x to initialize RAM and boot to Flash.
   2. Build the M3 application and load it into the M3 flash.
3. Select the C28x application. Build the C28x application and load it to the C28x Flash
4. In the C28x debug window: Close all open Watch windows and Memory windows which can read any address in Flash.
   • This will make make sure debugger reads do not power on the flash by performing a read.
5. Terminate the debug session. This will also save the workspace.

Create a Flash Boot Target Configuration

It is important that the C28x GEL file used by Code Composer Studio not interfere with the debug process. To avoid this, create a target configuration that does not include the C28x GEL:

1. Create a new target configuration and name it appropriately
   
   ::
   

   Create a new target configuration
2. Select the debugger (in this case the XDS100v2) and the device
   
   ::
   

   Select the debugger and device.
3. Select the advanced tab
4. Select the C28x
5. Remove the C28x GEL file
6. Save the Target Configuration.
   
   ::
   

   Remove the C28x GEL file and save the configuration.

Launch Code Composer Studio and Start the C28x Application

1. Launch Code Composer Studio using the dual boot target configuration created in the previous step.
2. Connect to both the M3 and C28x.
3. Perform a debug reset on both the M3 and then on the C28x.
4. Run the C28x CPU and then halt it
   • In the C28x disassembly window the program counter (PC) should stop at an IDLE instruction.
   • If the PC does not stop at the IDLE instruction, then you still have a memory window, watch window or GEL script which reads C28x FLASH memory.
   • If the C28x PC is at the IDLE instruction, then everything is correct and you can continue
   • Run (Resume) the C28x CPU

Start the M3 Application

1. M3 sub-system: load your application symbols
2. Add a break point after the Flash init completes and before sending the boot command to C-Boot ROM
   
   ::
   

   Break on the IPC command.
3. RUN the master CPU (M3) application.
   • Did the M3 stop at the break point? If it did, then everything is working correctly.
   • If the M3 does not stop at the breakpoint, then halt the M3 and see where it stopped.
     • The likely cause is the boot MODE pins. The M3 boot ROM logs the boot status at the first location in C2 RAM, which is location 0x20004000. If the boot pins are set for boot to Flash, then bit 3 of 0x20004000 will be set.
     • Next check the CTOMIPCBOOTSTS register. This register is used by the C28x ROM to communicate boot status to the master M3 subsystem.

Running Dual-Core From RAM

Running dual core examples from RAM is possible, but can be tricky to do a proper RAM boot while running through the bootROM.

The GEL files in Code Composer Studio effectively take care of the functions the bootROM would normally perform on a standalone flash boot. When running from RAM, the code should not call the IPC Boot function. This will prevent the M3 from hanging on the boot function and would allow you to run both core manually without making any modifications to the GEL files.

Frequently Asked Questions

Q: Help me understand the boot switches on the controlCARD

A: When viewing the controlCARD in the docking station, SW1 is the boot mode switches. By default each of the boot pins are pulled up. Turning the dip switch on (up position) connects the respective GPIO to a strong pull down. Given the pin 1 indicator on the board and what pin 1 is connected to in the schematic, the switches correspond to GPIO 34, 35, 47, and 43 from left to right.

Note: For SW1 with the switches in the up position (on) ties the pin to a strong pull down which will be a “0” on the table. That is, on position “0” and off position “1”.

Q: Is this flow correct?

I have code loaded to both the M3 and C28. It looks like the M3 boots fine and I can reset it and run using CCS. For the C28, I can do a reset and get to the beginning of the boot ROM (just like a standard C28x device), and when I run it stays at an IDLE instruction (IDLE mode) – which I think is correct. If I understand it properly, the M3 needs to send a IPC command to exit the IDLE, which is different from the M3 releasing the C28 from reset. What needs to be done to release it from IDLE? Is this some code that needs to be added, or run a script in CCS?

A: You are correct that when you boot the C28x the bootROM should maintain control and should sit in idle. You are also correct that the M3 has to send a boot command to the C28 over IPC and that releasing the c28x from reset is in fact different. The M3 bootROM releases the c28 from reset at boot time, so most users should never need to do this. To boot the C28x from the M3 you will need to execute this function in your application:

//    
//  Send boot command to allow the C28 application to begin execution
//
    IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

Q: What is the equivalent IPC command for boot to RAM?

//
//  Send boot command to allow the C28 application to begin execution
//
    IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_RAM);

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