Cortex-M3 Device Cycle Accurate Simulator

From Texas Instruments Embedded Processors Wiki

This is a cycle accurate simulator which models the ARMv7-M architecture. It is used to develop and debug software for Cortex M3 processor. This simulator is available as part of the CCS IDE and supports a wide variety of features to debug and profile the application code.

List of Architecture features modeled

• ARMv7-M instruction set
  
• Nested Vectored Interrupt Controller (NVIC) :
  Configurable from 1-240 physical interrupts; up to 256 levels of priority
  Non-Maskable Interrupt (NMI)
  tail chaining, late arrival service & stack pop pre-emption
  Nesting (stacking) of interrupts
  Dynamic interrupt reprioritization
  
• Memory Protection unit (MPU) :
  Optional component for separation of processing tasks and data protection
  Up to 8 regions of protection; each of which can be divided into 8 sub-regions
  Region sizes between 32 bytes to the entire 4 gigabytes of addressable memory 
  
• Integrated sleep modes :
  Sleep Now mode for immediate transfer to low power state
  Sleep on Exit mode for entry into low power state after the servicing of an interrupt
  
• Memory :
  Up to 4 gigabytes of addressable memory space
  Unaligned data storage and access 
  
• System timer (SysTick) Enables running of BIOS based applications. 
  
  

Debug and analysis features supported 

• Function profiling: The following CPU event counts are available for profiling the code.
  

    - Instruction 
         o decoded - Number of instructions which got decoded.
         o condition_false - The number of instructions that have not been executed because the condition predicate evaluated to false.
                                    This includes instructions killed within If-Then block

   - NOP – Number of nop instructions executed

   - sleep – Number of sleep instructions executed

   - wakeup – Number of times CPU woke from sleep. 

    - fault_escalation - Number of times fault got escalated to hard fault.

    - Discontinuity
           o Exception
                 NMI
                 PendSV
                 SVcall
                 SysTick
                 Bus_fault
                 Hard_fault
                 Mem_manage_fault
                 Usage_fault
           o Interrupt – The following events are available for each interrupt.
                 ISR_entry
                 ISR_exit
                 ISR_missed
                 ISR_pending

• Watch points
  
•  Code coverage
  
• Intuitive simulator setup - Used for the following :
   o Chosing the functional variant of the simulator..
   o Turning MPU on and off
   o Chosing the endianness between Little Endian , Big Endian and Big Endian (BE-8)
   o Selecting number of interrupt lines

Memory map
The entire address range is modeled as flat memory except the following :

• System Control Space (0xE000E000 to 0xE000EFFF)
• Bit band regions
          Peripheral bit band alias region (0x42000000 – 0x43FFFFFF)
          SRAM bit band alias region (0x22000000 – 0x23FFFFFF)

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