Cortex-R4 CPU Functional Simulator

From Texas Instruments Embedded Processors Wiki

Cortex-R4 CPU Functional Simulator

This simulator is a Cortex-R4 CPU only simulator and it's a functional simulator. This is simulator comes with a flat memory attached to the external bus; Mainly used in algorithm development where the development is CPU centric.

Features

• Integrated with Code Composer Studio with unified loader support for both Microsoft Windows and Linux platforms
• Pin connect for injecting interrupts to peripherals
• Advanced profiling
• Ease of configuring the simulator through enhanced Code Composer Studio setup
• Endianness (Little, Big, BE-8: byte invariant; and BE-32: word invariant)

Limitations

• No cycle information
• Does not support Code Composer Studio advanced debug and analysis features.
• Java state is not supported.

The following components are not modelled

• MPU. No memory maps; entire memory is treated as a flat memory with 0 latency
• FPU
• Buses, Caches and buffers
• ARMv7R instructions for multi-core environment (event handling). They are treated as NOP’s
• Co-processor instructions for other than move instructions for CP15 registers. They are treated as NOP's
• Exclusive load/store instructions are treated as normal load/store instructions. Monitor is not modeled, hence instructions, other than load/store, using the monitors are treated as NOP’s.

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