From Texas Instruments Embedded Processors Wiki

The Cortex M3 is a an ARMv7-M microcontroller core. It supports only the Thumb2 instruction set. Its implementation uses a 3-stage pipeline with a modified Harvard architecture, and incorporates features like branch speculation, single cycle multiply and hardware divide. Design goals include providing 32-bit performance for deeply embedded systems, at the memory costs expected of 8 to 16-bit devices.

Architecture Highlights

For a detailed overview, see the Introduction to Cortex-M3 white paper listed later.

As a microcontroller core, the Cortex-M3 is optimized differently from parts like the Cortex A8. For example, it does not include SIMD or floating point support. It includes a short 3 stage pipeline instead of a long 13-stage one, minimizing costs of pipeline disruptions (including IRQs); and is not superscalar (there is no instruction-level parallelism). Virtual memory is not supported, although there is an optional Memory Protection Unit. Instead of supporting instruction or data caches, it optimizes for single cycle execution from on-chip flash or SRAM. Only the stack pointer register is shadowed.

The M3 integrates a few essential peripherals. This helps it optimize for fast deterministic IRQ response, and minimizes implementation-specific differences in core lowlevel code. One peripheral is a prioritized interrupt controller, the "NVIC", which is tightly coupled to the core. It supports nested IRQs and up to 240 external interrupt vectors as well as several system vectors. One of the system vectors, PendSV, is often used to trigger task switching. Another system vector supports the standard "SysTick" system timer, used most often to generate periodic timer interrupts and to support timesliced task preemption.

Cortex-M3 parts build on knowledge from earlier ARM based microcontrollers, such as the popular ARM7TDMI. Using only Thumb2 instructions removes the need for dual mode (ARM or Thumb) operation, and thus simplifies the software environment and tuning. The resulting code can be notably faster than Thumb-only code, and only slightly slower than ARM-only code. As a superset of Thumb, its dense code makes better use of limited memory bandwidth than Thumb-only or combined Thumb-and-ARM code bases. Compared to ARM7TDMI, the Cortex-M3 gets more MIPS-per-MHz, and consumes about 2/3 the power at the same clock rate. Power demands are further reduced by clock gating during the WFI instruction.

In addition to Thumb2, three other mechanisms help support dense code. One is the addition of new Thumb2 instructions; compare-and-branch combines two instructions, while bitfield operations combine a series of shift-and-mask instructions. Another is hardware support for bit banding, where address aliases support single instruction atomic reads or writes of single bits in portions of the SRAM and I/O controller address spaces (which might otherwise need an interruptible read/modify/write triplet). The third is optional support for unaligned data access, loosening data alignment restrictions.

Useful Documentation

Public documentation from ARM Ltd can be browsed on-line at the ARM Information Center. PDF versions of particularly useful documents are:

• Introduction to Cortex-M3 white paper
• ARMv7-M Architecture Reference Manual (requires a web account) covers the instruction set, exception handling, built-in peripherals such as the NVIC and SysTick, debug support, and more
• Cortex-M3 TechnicalReference Manual (r2p0, r1p1) covers debug support (including code tracing and profiling), MPU, memory map, and more
• Application Note 179 (entitled Cortex™-M3 Embedded Software Development) may be of interest, especially if you are converting code from earlier ARM processors.

In addition you will need a vendor-supplied chip-specific manual, such as the data sheet for the Texas Instruments Stellaris® LM3S3748 Microcontroller, for details about how the Cortex-M3 integrates with system-on-chip peripherals, manages power up and resets, and so forth.

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