DM36x system optimization
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DM36x System Optimization
DM36x is used to host various video based application. This topics details the few methods that can be adopted to improve the system level performance on DM36x.
DDR timing
The value of the below registers can affect the performance of the system. Hence, it is advised to review the value of these registers and should be kept at the most optimized value. There is no specific recommended value, as the value will change depending on the DDR used in the product. For details please refer to : [SPRUFI2 http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprufi2&fileType=pdf ]
DDR->SDTIMR DDR->SDTIMR2 DDR->SDBCR DDR->SDRCR
MASTER Priority
The master priority registers needs to be modified as below. For details, please refer to [SPRUFG8C http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprufg5a&fileType=pdf] for details on meaning of this register. Please note that the below setting may increase the ARM load for a given application, hence should be used when there is headroom for ARM load.
MSTPRI0 : 0x1c4003C = 0x440022
Resizer registers
Optimized settings for DDR access of resizer. For details, please refer to [SPRUFG8C http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprufg8c&fileType=pdf] for details on meaning of this register.
0x01C7:0420h (DMA_RZA SDRAM Request Minimum Interval for RZA) = 0x40 0x01C7:0424h (DMA_RZB SDRAM Request Minimum Interval for RZB) = 0x40
All OSD related DMA tranfer should happen on TC1/QUEUE1.
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