DM643x/DM6446 VPSS buffer overflow problem

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Objective

On the DM643x and the DM6446 there is a potential risk that the write buffer of the CCDC controller of the Video Processing Subsystem (VPSS) runs into an overflow condition in some cases. The following article describes the contributors to this problem, provides several possible containment actions, and describes a procedure of how the detect and escape from this overflow state.

Root cause description

The fundamental root cause behind this problem is that the SDRAM/DDR2 controller may not be able to fetch the video data from the VPSS in time, when there is a high video data rate and high DDR2 load. This could result in a memory overflow of the write buffer in the CCDC controller, i.e. all data units have been filled and not yet transferred to SDRAM/DDR2 before the next data unit is to be filled. This condition is indicated by the setting of the "CCDC_WBL_O" bit of the "VPSS Peripheral Control Register" (PCR). Once this overflow occurs, the Video Port stops outputting new video data, but continues to generate interrupts. This is a permanent overflow state that can only be cleared by using a certain procedure as described below.

The orange arrows in Figure 1 highlight the data path from the video input to the SDRAM/DDR2 memory:

Figure 1: Data path through VPSS

Containment measures

There are several contributors to the occurrence of this problem. Since we know these contributors, we can configure the corresponding modules in our system in such a manner, that the probability of this issue could be reduced. Therefore please consider the following recommendations:

Reduce non-time critical EDMA priorities below the EDMA priority of the video port.
Reduce the "PR_OLD_COUNT" value in the Peripheral Bus Burst Priority Register (PBBPR). This value indicates the maximum number of 32-byte DDR2 burst transfers that can go through before the DDR2 memory controller raises the priority of the oldest request in the queue. Please refer to section 2.1.1 of the TMS320DM6437/35/33/31 Errata document [1] for additional information. The negative impact of reducing this value (some applications needed a setting as low as 0x3) is that the available DDR2 bandwidth is reduced.

Detecting and escaping from an overflow state

The following procedure could be used to determine that the system is in "overflow state" and to escape from this state:

Write a magic word (e.g. 0x80808080) to the end of the DDR2 buffer before this buffer is handed over to the VPFE driver.
Writeback-invalidate the data from cache to DDR2 memory (e.g. via a BCACHE_wbInv() call).
Pass the buffer to the VPFE driver to let the video port hardware fill the buffer in the normal way.
When the buffer is returned from the VPFE driver, check whether the magic word has been overwritten. In the failure case, the magic word could still found in the buffer after the driver has passed it back to the application. When this happened, the CCDC_WBL_O flag in the PCR register indicates the overflow condition.
To escape from this overflow state a PSC reset needs to be asserted and all VPFE registers need to be re-initialized, by going through the process of calling the various initialization functions of the PSP driver.

References

http://www-s.ti.com/sc/techlit/sprz250

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