PCI Interrupt Handling on DM6467/DM6467T PCI Host

From Texas Instruments Embedded Processors Wiki

This page is currently under construction. The content of this page is due to change quite frequently and thus the quality and accuracy are not guaranteed until this message has been removed. Please feel free to contribute to this page while construction is in progress.

		Wiki Note
PCI Interrupt Handling on DM6467/DM6467T PCI Host
Author(s):Hemant Pedanekar		Texas Instruments
SPRWIKI9071		July 2011
Abstract
This application note describes the hardware and software modifications required to support PCI interrupts on DM6467 (and DM6467T) Evaluation Module (EVM) set up as PCI Host.
Contents 1 OVERVIEW 2 SETUP 3 Considerations 4 Hardware Modifications 5 Software Modifications 5.1 Taking Care of Pin Multiplexing 5.2 Setting up GPIO Interrupts 5.3 Adding Interrupt Allocation Support in PCI Host Driver

OVERVIEW

DM6467/DM6467T devices do not have PCI interrupts input lines (INTA, INTB, INTC, INTD). Thus the default EVMs cannot receive PCI interrupts from targets connected over the bus and in turn, cannot interrupt DM6467 ARM on the same.

This can be worked around by using GPIO lines to receive PCI interrupts from the PCI slot to which DM6467 PCI Host EVM is connected. This requires using wires to get the INTA...D lines from the slot and connect them to DM6467 GPIO lines and modify the Host Controller driver accordingly.

SETUP

The hardware setup involves following:

1. DM6467 EVM
2. PCI back-plane with at least 2 PCI slots

• Put DM6467 EVM in one slot
• Connect at least one PCI card (e.g., an Ethernet NIC) in the other slot to be used as PCI target device

Considerations

To enable DM6467 to receive PC interrupts, we will designate GPIO pins. As per PCI specification, upto 4 interrupts can be wired to receive interrupts from PCI target devices. Thus we will need to use 4 GPIO pins which would generate interrupts to DM6467 ARM.

Note following points regarding the GPIO:

• GPIO0-7 (Bank 0) can be set up as individual interrupt sources
• GPIO2 and GPIO3 are muxed with audio clock 1 and 0 respectively so we need to set up pinmux configuration for GPIO function on this pins and disable AUDCLK0 and AUDCLK1.
• GPIO interrupts should be set up for rising edge

Hardware Modifications

Use wires to connect PCI interrupt lines from target device(s) from respective slots to DM6467 PCI Host's GPIO pins.

Following figures show 2 of the possible arrangements when using 4 target devices:

The approach shown in Fig 1 is useful when the PCI targets used support more than one interrupt.

Note: The arrangement in Fig 2 assumes that all the PCI target devices used use single interrupt (INTA).

Software Modifications

This section describes the modifications required in DM6467 PCI Host Controller driver and DM6467 EVM specific file to incorporate the interrupt handling support for PCI Host.

Please note following points regarding the software modifications discussed in later subsections:

1. The source code referred here is based on kernel from arago git repository available here
2. For software support, we consider the approach shown in Fig 1 in earlier section

Taking Care of Pin Multiplexing

File: arch/arm/mach-davinci/board-dm646x-evm.c Function: dm646xevm_pci_setup

Add following line to disable AUDCLK0 to be able to use GPIO3 just before the if block.

 davinci_cfg_reg(DM646X_AUDCK0);

Note that a similar configuration of AUDCLK1 (for GPIO0) already exists inside the if block. In case the if block is not being executed in your case, following line also needs to be added:

 davinci_cfg_reg(DM646X_AUDCK1);

Setting up GPIO Interrupts

Now we need to set up GPIO bank 0 interrupt, pin direction (input) and trigger (rising edge). For this, add following code after the if...else block in dm646xevm_pci_setup():

 set_irq_type(gpio_to_irq(0), IRQ_TYPE_EDGE_RISING);
 set_irq_type(gpio_to_irq(1), IRQ_TYPE_EDGE_RISING);
 set_irq_type(gpio_to_irq(2), IRQ_TYPE_EDGE_RISING);
 set_irq_type(gpio_to_irq(3), IRQ_TYPE_EDGE_RISING);

Note that rest of the things for setting up GPIO IRQs will be taken care by GPIO IRQ layer in kernel.

Adding Interrupt Allocation Support in PCI Host Driver

The interrupt allocation is directly related to how the interrupt routing is done from target devices to DM6467 host. We consider the setup shown in Fig 1.

Also, the numbers populated for irqs in the table should be same as the output of gpio_to_irq() call for respective GPIOs.

File: arch/arm/mach-davinci/pci-dm646x.c Function: dm646x_pci_map_irq

Add following code after removing return -1 statement:

	int irq = -1;

	static int dm6467_pci_irq_tbl[4] = {
		48,
		49,
		50,
		51
	};

	irq = dm6467_pci_irq_tbl[(pin - 1) & 3];

	return irq;

Leave a Comment