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DM816x C6A816x AM389x Overview

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Landing page for DM816x, C6A816x and AM389x Product Families


Availability Disclaimer

DM816x products are intended for high-volume OEMs and ODMs developing video security, video conferencing, video phones and thin/zero client applications. For other customers, design support is available for DM816x-based products through authorized TI third parties, listed here. For additional information on our video security solutions, please visit our IP network camera and DVR/NVRpages.

TI does not recommend C6A816x for new designs (NRND). TI recommends that customers purchase DM816x or AM389x solutions, which are pin-to-pin and software compatible devices to the C6A816x devices. DM816x provides equivalent ARM® and DSP performance with the addition of HD video acceleration. AM389x provides equivalent ARM® performance. Please see the DM816x and AM389x pages for more information.

Important Documentation

Refer to the EZ 1-2-3 Design Companion wiki pages:

Key Documentation

Application Notes

Block Diagrams

DM816x SW Architecture BlockDiagram.jpg

C6A816x SW Architecture BlockDiagram.jpg

AM389x SW Architecture BlockDiagram.jpg


Product Matrix

For a general overview of TI's ARM portfolio, see the ARM Platform Technical Guide Brochure.

Also take a look at the DSP & ARM MPU Selection Tool for help choosing a processor.

For a comparison between ARM9, ARM11 and Cortex-A8, take a look at this matrix.

All devices have the CYG package option.

AM3894 AM3892 C6A8168 C6A8167 DM8168 DM8167 DM8166 DM8165
Cortex-A8 Processor Up to 1.5 GHz Up to 1.5 GHz Up to 1.2 GHz
C674x DSP None Up to 1.25 GHz Up to 1.0 GHz
HDVICP2 Video Accelerator None None 3: Up to 600 MHz 2: Up to 600 MHz
SGX530 3D Graphics Accelerator Up to 375 MHz None Up to 375 MHz None Up to 333 MHz None Up to 333 MHz None

Device Speed Range Table

Devices PN Code ARM (MHz) DSP (MHz) HDVICP2 (MHz) SGX530 (MHz)
DM816x 0 720 667 450 240
DM816x,C6A816x,AM389x Blank 1000 800 533 333
DM816x 1 1000 1000 533 333
DM816x,C6A816x,AM389x 2 1200 1000 600 300
C6A816x,AM389x 5 1500 1250 NA 375

See Device Nomenclature in datasheet and Parametrics table in product folders for speed ranges supported for each specific part number.

Silicon Reference

Schematic and Layout Guidelines

EVM Documentation and Design Resources

  • Base Board: Rev G DDR3 EVM
  • The only change on Revision G is the SPI Flash (U20) changed from W25X32VSFIG to W25Q32BVSFIG
  • Starting with Revision G of the EVM, version information is stored in a user accessible I2C EEPROM on the main board at EEPROM address 0 (I2C address 0x50). Details are available in the EVM FAQ.
  • The only change on Revision F is the DM8168 device is marked differently:
    • Rev F: TMS320DM8168ACYG2
    • Rev E: TMX320DM8168ACYG
  • Side-by-side Comparison of Rev B and Rev E EVM Schematics: File:TI816xEVM RevB to RevE Compare.pdf
    • Major changes to EVM schematics:
      • Move to Micron DDR3 from Elpida; made change to address DDR VTT power supply sequencing issue – pages 21 and 53
      • Changes to capacitors around TPS65232, and improvement to capacitor placement in the layout, to avoid electrical overstress of TPS65232 – page 51
      • Changes to resistors for AVS control and to pull GPIO3 low – page 54
      • Use of AVS enabled DM8168 devices
      • Capacitor change to address USB VBUS power supply sequencing issue – page 56
      • Resistor change to fix PCIe Reset issue – page 28
      • Also refer to Revision History on last page of EVM schematics.
  • Expansion I/O Daughter Card: Rev C I/O Dcard
  • EVM HW Mods for AVS

Symbols, Footprints, and Simulation Models

  • IBIS simulation model
    • Preliminary version is on this Forum thread: [1]
    • Final version is TBD

Thermal Use Cases

  • A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability.
  • Refer to appendix C of FCBGA Packaging application note (TBD) for thermal modeling results.

SW Overview


SW Development Tools

Code Composer Studio


  • Rowboat is a community portal for Android on TI ARM® Cortex™-A8 platforms
    • A completely free, open-source project for all customers, developers, and third parties
    • Supported by TI Development team
    • Android base port and graphics support available for TI EVMs and Community boards on rowboat.
    • Includes: Code (binary and source), WiKi, How-to’s, links, IRC, FAQs, and more
  • TI Android Development Kit
    • Derived from rowboat to aid customer development and out of the box experience.
    • Stable periodic snapshots (approx. every 6 months) available on
    • Tested by TI quality assurance team
    • Includes product specific documentation
  • Commercial support for Android developers is available from Mentor Graphics

FAQs and Other SW Reference Information

Peripheral Overview

Microprocessor Unit (MPU) Subsystem

The MPU subsystem integrates the following modules
ARM subchip

  • ARM® Cortex™-A8 core
    • ARM Version 7™ ISA: Standard ARM instruction set + Thumb®-2, Jazelle® RCT Java accelerator,
      and media extensions
  • NEON™ SIMD coprocessor (VFP lite + media streaming instructions)
  • Cache memories
    • Level 1: 32KB instruction and 32KB data—4-way set associative cache, 64 bytes/line
    • Level 2: 256KB L2 cache.
  • Interrupt controller with synchronous interrupt lines
  • Asynchronous interface with core logic
  • Debug, trace, and emulation features: ICE-Crusher, ETM, ETB modules.

For additional details on CortexA8 click here

C674x DSP Subsystem (DM816x and C6A816x only)

  • The DSP Subsystem integrates the following modules:
    • C674x DSP CPU
    • 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Code (EDC)
    • 32KB L1 Data (L1D)/Cache (up to 32KB)
    • 256KB L2 Unified Mapped RAM/Cache with Error Correction Code (ECC)

High Definition Video Image Co-Processors (DM816x only)

  • Up to three programmable High Definition Video Image Co-Processing Engines (HDVICP2 or also referred to as IVA-HD)
  • Supports a range of Encode, Decode, and Transcode Operations
  • Supports main video codec standards in HW; initial codecs supported in SW are H.264 encode/decode
  • Each engine can support 1 1080p60 or 2 1080p30 or 4 720p30 or 10 SD video encodes/decodes

Memory Management Units (MMU)

The device contains these memory management units (MMU):

  • Host ARM subsystem Cortex A8 MMU
  • HDVPSS Controller MMU
  • DSP/EDMA Shared System MMU (DEMMU) -- DM816x and C6A816x only
  • Dynamic Memory Manager (DMM)

Enhanced DMA controller (EDMA)

On-chip Enhanced DMA controller (EDMA) supports 4 simultaneous physical channels and up to 64 programmable logical channels

Interrupt Controller (INTC)

The device has one interrupt controller (INTC) module.

General-Purpose Memory Controller (GPMC)

  • 8-/16-bit Wide Multiplexed Address/Data Bus
  • Up to 6 Chip Selects With 128M-Byte Address Space per Chip Select Pin
  • Glueless Interface to NOR Flash, NAND Flash (With BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
  • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
  • Non-multiplexed Address/Data Mode

EMIF (External Memory Interface)

  • The device has a dedicated interface to DDR3 and DDR2 SDRAM. It supports JEDEC standard-compliant DDR2 and DDR3 SDRAM devices with the following features:
    • 16-bit or 32-bit data path to external SDRAM memory
    • Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, and 2Gb devices
    • Two interfaces with associated DDR2/3 PHYs
    • Dynamic memory manager allows for interleaving of data between the two DDR interfaces.
    • Supports the following CAS latencies:
      • DDR2: 2, 3, 4, 5, 6, and 7
      • DDR3: 5, 6, 7, 8, 9, 10, and 11

On-Chip Memory Controller (OCMC) Subsystem

512K-Bytes On-Chip Memory Controller RAM

SGX530™ Graphics Accelerator - Only in certain devices

The SGX530™ Graphics Accelerator subsystem accelerates 3-dimensional (3D) graphics applications. The SGX subsystem is based on the core from Imagination Technologies. The SGX graphics accelerator efficiently processes a number of various multimedia data types concurrently. The SGX subsystem is connected by a 64-bit master and a 32-bit slave interface to the L3 interconnect. The getting started guide for Graphics SDK is here -- TBD.

HD Video Processing Subsystem (HDVPSS)

Provides high quality display processing, digital video inputs and outputs, HDMI 1.3 transmit, and simultaneous HD/SD analog output with OSD. Refer to the device datasheet and TRM for more details on HDVPSS features.


The device includes several types of timers used by the system software, including 7 general-purpose timers (GP timers) and one watchdog timers (WDT).

UART/IrDA/CIR Overview

The processor contains three universal asynchronous receiver/transmitter (UART) devices controlled by the microprocessor unit (MPU).

Inter-Integrated Circuit (I2C) Module

The device contains two multimaster high-speed (HS) inter-integrated circuit (I2C) controllers (I2CI modules, where I = 1, 2), each of which provides an interface between a local host (LH), such as the MPU subsystem, and any I2C-bus-compatible device that connects through the I2C serial bus. External components attached to the I2C bus can serially transmit/receive up to 8 bits of data to/from the LH device through the 2-wire I2C interface. Each multimaster HS I2C controller can be configured to act like a slave or master I2C-compatible device.


The multichannel serial port interface (McSPI) is a master/slave synchronous serial bus. There is one McSPI module in the device.


The multi-channel buffered serial port (McBSP) provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips (digital base band), audio and voice codec (AIC23 device), etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.

The device provides one instance of the McBSP module.


The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

The device includes three multichannel audio serial port (McASP) interface peripherals (McASP0, McASP1, and McASP2). The McASP0 module has six serial data pins, while McASP1 and McASP2 are limited to two serial data pins each.

Secure Digital/Secure Digital I/O (SD/SDIO) Card Interface

The processor contains one secure data/secure digital I/O (SD/SDIO) host controller which provides an interface between a local host (LH) such as a microprocessor unit (MPU) or digital signal processor (DSP) and either SD memory cards or SDIO cards and handles SD/SDIO transactions with minimal LH intervention.

In order to create a bootable SD card under Linux compatible with device boot ROM, follow the instructions in the SDK User Guide.

Universal Serial Bus (USB)

The device includes two USB ports with integrated 2.0 PHY.

  • Supports USB 2.0 peripheral at speeds HS (480 Mb/s) and FS (12 Mb/s)
  • Supports USB 2.0 Host at speeds HS (480 Mb/s), FS (12 Mb/s), and LS (1.5 Mb/s)
  • Supports all modes of transfers (control, bulk, interrupt, and isochronous)
  • Supports high bandwidth ISO mode
  • Supports 16 transmit (TX) and 16 receive (RX) endpoints including endpoint 0

General Purpose I/O (GPIO) Interface

The general-purpose interface combines six general-purpose input/output (GPIO) banks.

Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 192 (6 x 32) pins.

These pins can be configured for the following applications:

  • Data input (capture)/output (drive)
  • Keyboard interface with a debounce cell
  • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations.
  • Wake-up request generation in idle mode upon the detection of external events.

These modules do not include pad control (pull up/down control, open-drain feature).

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC subsystem module and is considered integral to the EMAC/MDIO peripheral.

The EMAC module is used to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol.


  • One PCI Express 1.0/2.0 compliant link with up to two lanes in each direction
  • Capable of operating as a Root Complex (RC) or single function Endpoint (EP)
  • Expandable beyond point-to-point connections via industry standard switches


  • GEN2 SATA-AHCI Controller (2 Host Bus Adaptor (HPA) Ports)
  • Supports GEN2 (3 Gbits/Sec) and GEN1 (1.5 Gbits/Sec) speeds per port
  • Supports capability of being attached to a Port Multiplier to extend/de-multiplex a single HBA port to 15 Port-Multiplier-Port (PMP)


  • Supports SmartReflex™ Technology (Level 2)
    • Based on the device process, temperature, and desired performance, the SmartReflex™ module advises the host processor to raise or lower the core 1-V supply voltage for minimal power consumption. The communication link between the host processor and the external power regulator can be accomplished using GPIOs or I2C.
  • Device REQUIRES use of Adaptive Voltage Scaling (up to 32 linear voltage steps, minimum of 8 steps) for proper device operation.
  • AVS Driver Guide

Development and Reference Designs

Development Boards

  • EVM - Details on the evaluation module can be found on the EVM page.

Power Companion Reference Design

Reference Designs

  • Z3-DM8168-MOD is a compact OEM-ready module from Z3 Technology based on the DM8168.

Related End Equipments

The links at the TI website below provide block diagrams, application notes, tools, software, design considerations, and other related information for various Video and Imaging end-equipment products.

Training Material

  • High-level overview videos are available today in the product folders.
  • TI816x One-day Workshop
  • Additional online modules and seminars will be available starting in late 3Q11. Details will be posted on


  • What are some advantages of these device families?
    • Pin for Pin compatible set of devices for design flexibility
      • The DM816x, C6A816x and AM389x device families are all pin for pin compatible
      • AM389x, DM816x and C6A816x are software compatible.
    • Up to 50% reduction in system cost due to high integration
      • Memory Controller support DDR2/DDR3 providing flexibility to choose memory
      • Integrated USB PHYs, SATA PHYs, PCIe PHY, HDMI TX PHY.
  • How can I estimate Power required for my application using these processors?
  • How can I determine which product in the DM816x, C6A816x and AM389x families is the best choice?
    • Target Applications:
      • DM816x: Video Security, Video Conferencing, Video Infrastructure, Media Server, Digital Signage
      • C6A816x: Machine/Industrial Vision, High End Test and Measurement, Tracking and Control, Medical/Biological Imaging
      • AM389x: Single-board computing, Network & Comms Processing, Industrial automation, Human Machine Interface, Interactive POS kiosks
    • Please refer to the Product Matrix to see the different features supported by each device.
  • What are key care abouts for board design?
    • Please refer to Schematic Checklist for general checklist to ensure device connectivity as well as key items to be addressed.
    • Please refer to the routing, design and layout specifications in the following sections of the datasheet: DDR, SATA, PCIe, USB, HDMI, and Video DAC.
  • How can I determine if these devices would be able to meet my feature needs with the existing pin mux?

Useful Links

For access to pre-release documents, please contact Tom Ballew at