Digital I/O (MSP430)

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Configuring GPIOs

The pins which have GPIO functionality (see device pinout) can be selected by configuring the below register settings:

PxSEL should be set to zero for the bit corresponding to the port desired in this register.

If you are configuring an output for that pin...

PxDIR should be set to 1 for output for the bit corresponding to the port desired in this register.

PxOUT should be set to 1 for output high or zero for low output state for the bit corresponding to the port desired in this register.

If you are configuring an input for that pin...

PxDIR should be set to 0 for input for the bit corresponding to the port desired in this register.

PxIN can then be read.

Each register represents a port, and each port has up to 8 pins available for I/O. So P1.x is represented with the registers P1DIR, P1SEL, P1OUT, and P1IN. Each bit in each port register represents a specific pin (i.e. for port 1, each bit represents each of P1.0, P1.1, ... , P1.7). The nomenclature for each register is as follows from MSB to LSB:

Px.7 Px.6 Px.5 Px.4 Px.3 Px.2 Px.1 Px.0

So if you wanted to set P1.4 to output direction you would set P1DIR |= 0x10;

If you are configuring the pin for it's peripheral functionality...

Let's use the example of the F1611, where P5.7 can be either a GPIO or a SVSOUT peripheral function. Let us configure this pin to it's peripheral functionality.

The P5SEL register controls whether or not the pin is set to GPIO or it's alternate peripheral functionality. Because of this we need to set the P5SEL bit corresponding to P5.7, since we want the peripheral functionality (not GPIO functionality). To summarize, enabling P5.7 as SVSOUT requires the following statement:

P5SEL |= 0x80; // which corresponds to the MSB of P5.x, which is P5.7

The above corresponds with the input/output schematic on page 57 of the device datasheet. For more information on configuring the MSP430 port pins please see section 9.2.4 of the User's Guide

For more information on all of these configurations see chapter 9, the Digital I/O section, of the MSP430x1xx User's Guide, SLAU049

GPIO Port Current

For Outputs

In all datasheets, there are four figures given (usually Fig 2-5). These figures specify the voltage drop across a port when a given current is sourced or sunk from/into a port. For example, when the port output is driven to a “1” (Voh), the output port voltage will depend on the amount of current sourced by the MSP430 port output to an external device. Per the datasheet (in the test conditions), if 1.5 mA is sourced by a port pin, the output High voltage will be within the given range.

Per the customer question: as long as the FET is high impedance, no current will be sourced into the MSP430 when there is a low on it (PxOUT=0), so the port voltage will stay close to 0V, per the VOL figure.

It totally depends on the customer's application as to how much current they want to source/sink on of a port pin and as result of that how much voltage drop can they live with.

For example, on Fig 8 (Voh, pg 26), the port pin can source 48 mA, but the voltage on that pin will be 0V, when the port is driven to a 1. This may be unacceptable in most applications.

For Inputs

On power up the GPIOs are configured as high impedance CMOS floating inputs. CMOS inputs sink or source only minute amounts of current (commonly called leakage current) because of the behavior of standard CMOS technology, which is voltage controlled instead of current controlled. As a result, this parameter always should have a maximum specification no greater than a few tens of microamperes. Please see the relevant spec on page 23 (current at any device terminal) and 27 (leakage) of the datasheet


Datasheet & this K-base Article