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Enhanced Direct Memory Access (EDMA3) Controller

Introduction

The enhanced direct memory access (EDMA3) controller in the Texas Instruments embedded processors is used to service user-programmed data transfers between two memory-mapped slave endpoints on the device. Common utilizations are:

• to service software driven paging transfers (for instance, from external memory such as SDRAM to internal device memory such as L2 SRAM)
• to service software or peripheral event driven data transfer between each of the core L2 SRAM of the embedded processor
• to service event driven peripherals, such as serial port peripheral like McBSP
• to perform sorting or subframe extraction of various data structures
• to offload data transfers from the main device CPU(s) or processor(s)

EDMA3 controller consists of two principal blocks:

1. EDMA3 channel controller (EDMA3CC)

The user interface for the EDMA3 controller, EDMA3CC includes parameter RAM (PaRAM), channel control registers and interrupt control registers. It prioritizes incoming software requests or events from peripherals, and submits transfer requests (TR) to the transfer controller.

1. EDMA3 transfer controller(s) (EDMA3TC)

Responsible for data movement, EDMA3TC issues read/write commands to the source and destination addresses programmed for a given transfer. However, the operation is transparent to the user.

Figure 1: EDMA3 Controller Block Diagram

EDMA3 Channel Controller (EDMA3CC)

EDMA3 Channel Controller (EDMA3CC) is the user interface for the EDMA3 controller. It services incoming requests/events by prioritizing them and submits transfer requests (TR) to the EDMA3TC. It provides a fully orthogonal transfer description up to three dimension transfers, independent indexes on source and destination, as well as chaining feature that allows 3-D transfer based on single event. There are two types of transfers available:

• A-synchronized transfers: one dimension serviced per event

• AB-synchronized transfers: two dimensions serviced per event

An EDMA3CC supports two types of channels:

• 64 Direct Memory Access (DMA) channels with event synchronization, manual synchronization (where CPU(s) write(s) to event set register) and chain synchronization (where a completion of one transfer triggers another transfer).

• 8 Quick DMA (QDMA) channels triggered automatically upon writing to a PaRAM set entry. These QDMA channels can also be used for programmable QDMA channel to PaRAM mapping.

Each of these channels (DMA and QDMA) is associated with a given event queue/transfer controller and a PaRAM set. DMA channels have higher priority than QDMA channels. Among these two groups, the lowest-numbered channel has the highest priority. There are 256 PaRAM sets present for channel transfer definition and each of them can be used for a DMA/QDMA channel, or link set. In addition, six transfer controllers/event queues with 16 event entries per event queue are provided and the system-level priority of these queues is user programmable. In addition, EDMA3CC allows flexible transfer definition with a choice of increment or FIFO transfer addressing modes, a more appropriate linking mechanism that allows automatic PaRAM set update and also chaining that allows multiple transfers to execute with a single event. Interrupt generations upon transfer completion or on error conditions also possible. Concerning the memory protection support, two types of memory protection exist; active and proxied memory protection. The first is used for TR transmission, whereas the second is for accesses to PaRAM and registers. Main blocks of EDMA3CC are PaRAM, EDMA3 event and interrupt processing register, completion detection, event queues and memory protection registers. Besides that, other functions in EDMA3CC include region registers and debug registers.

Main blocks in EDMA3CC

Figure 2: EDMA3CC block diagram

1. Parameter RAM (PaRAM)

EDMA3 controller is a RAM-based architecture. For this reason, the transfer context (source/destination addresses, count, indexes, etc.) for DMA/QDMA channels is programmed in a parameter RAM (PaRAM). Segmented into 256 PaRAM sets, each PaRAM set includes 8 x 4-byte PaRAM set entries, which includes DMA transfer parameters (source address, destination address, transfer counts, indexes, options, etc.). By default, all channels map to PaRAM set 0. PaRAM maintains parameter sets for channel and reloads parameter sets. It must be written in conjunction of the transfer context for the desired channels and link parameter sets. EDMA3CC processes sets on a trigger event and submits a TR to EDMA3TC.

Figure 3: PaRAM set

As stated above, PaRAM maintains parameter sets for channel and reloads parameter sets. The reload mechanism provided by the EDMA3CC, or linking, is used to reload the current PaRAM set upon its natural termination with a new PaRAM set. This mechanism is useful, especially for maintaining circular buffering and repetitive/continuous transfers without the CPU intervention. Upon completion of a transfer, the current transfer parameters are reloaded with the PaRAM set pointed to by the 16-bit link address field of the current PaRAM set. Another mechanism provided by the EDMA3CC is channel chaining. This mechanism allows triggering another EDMA3 channel transfer upon completion of an EDMA3 channel transfer. This method allows chaining several events through one event occurrence. Note that chaining is different when linking; EDMA3 linking reloads the current channel PaRAM set with the linked PaRAM set. Contrarily, the EDMA3 chaining does not modify or update any channel PaRAM set; it only provides a synchronization event to the chained channel. The example below shows that upon completion of EDMA3 transfers associated to the PaRAM set 3, the new PaRAM set is loaded (PaRAM set 255). Upon termination, the link is associated to a NULL set. When a PaRAM set associated with a channel is a NULL set, any future events on the same channel will be ignored by the EDMA3CC:

Figure 4: Linked transfer

1. EDMA3 event and interrupt processing register

It allows mapping of events to parameter sets, enable/disable events, enable/disable interrupt conditions, and clearing interrupts.

1. Completion detection

The completion detection block identifies transfers completion by the EDMA3TC and/or slave peripherals. Completion of transfers can optionally be used to chain trigger of new transfers or to assert interrupts. There are three modes of transfer completion informed to EDMA3CC: normal completion, early completion and dummy/null completion, applicable to both chained events and completion interrupt generations.

• • Normal completion

TCCMODE = 0 in OPT, the transfer or subtransfer is considered to be complete when EDMA3CC receives the completion codes from EDMA3TC. The completion code to EDMA3CC is posted by EDMA3TC after it receives a signal from the destination peripheral. This mode is typically used to generate an interrupt to inform the CPU that a set of data is ready for processing.

• • Early completion

TCCMODE = 1 in OPT, the transfer is considered to be completed when EDMA3CC submits TR to EDMA3TC. In this mode EDMA3CC generates the completion code internally. This mode is useful to allow subsequent transfers to be chained-triggered while the previous transfer is still in progress within EDMA3TC. This maximizes the overall throughput of the transfers\’ sets.

• • Dummy/Null completion

A variation of early completion, this mode is associated with a dummy set (a dummy set is a PaRAM set with at least one of the count fields is equal to 0 and at least one of the count fields is non-zero) or null set. In both cases, EDMA3CC does not submit the associated TR to EDMA3TC.

1. Event queues

Event queues block is the interface between the event detection logic and the transfer request submission logic. Each queue is 16 entries deep; thus a maximum of 16 events can be queued per event queue. However, if there are more than 16 events, these events remain set in the associated event register and the CPU is not stalled. There are six event queues in the embedded processor C6474. Each event in Queuen results a submission of its associated TR to TRn. Each event queue is serviced in a FIFO order.

1. Memory protection registers

The memory protection registers define the accesses (privilege level and requestors(s)) allowed to access the DMA channel shadow region view(s) and regions of PaRAM. Two kinds of memory protection supported by the EDMA3 channel controller: active and proxied.

• • Active memory protection

Read/write accesses by any EDMA3 programmer to the EDMA3CC registers to be accepted/denied based on user-programmed permission characteristics, set in memory protect permissions attribute (MPPA) registers, available in all EDMA3 regions.

• • Proxied memory protection

It allows a DMA transfer programmed by a given CPU (or EDMA3 programmer) to have its permissions travel with the transfer through the TR and also through EDMA3TC for the read/write transfers to the source and destination endpoints. This mode is activated by setting the EDMA3 programmer\’s priv value in the PRIV bit (supervisor versus user) and privid values PRIVID bit in the channel options parameter (OPT). The PRIV is 0 for user level and the CPU has a privid of 0. Other functions in EDMA3CC are region and debug registers.

Region registers

EDMA3CC memory-mapped registers are divided in three main regions:

• • Global region

Located at a single/fixed location in the EDMA3CC memory map, registers in this region control EDMA3 resource mapping and provide debug visibility as well as error tracking information.

• • Global shadow region

It is the region where only the channel registers (including DMA, QDMA and interrupt registers) are accessible.

• • Shadow region(s)

EDMA3CC allows partitioning of the resources between different masters via the shadow regions. Shadow regions registers allow DMA resources (DMA/QDMA channels registers, TCC and interrupts) to be assigned to unique regions in a mutually-exclusive way. These regions are owned by different EDMA3 programmers and this allows an autonomous operation for each master. There are eight regions in the embedded processor TMS320C6474. Debug registers Debug registers allow debug visibility by providing registers to read the queue status, controller status and missed event status.

Types of EDMA3 transfer

An EDMA3 transfer is defined in terms of three dimensions:

• 1st dimension or Array: The 1^st dimension in a transfer consists of ACNT contiguous bytes.

• 2nd dimension or Frame: The 2^nd dimension in a transfer consists of BCNT arrays of ACNT bytes. Each array transfer in the 2^nd dimension is separated from each other by an index programmed using SRCBIDX (number of bytes between arrays in source) or DSTBIDX (number of bytes between arrays in destination).

• 3rd dimension or Block: The 3^rd dimension in a transfer consists of CCNT frames of BCNT arrays of ACNT bytes. Each transfer in the 3^rd dimension is separated from the previous by an index programmed using SRCCIDX (number of bytes between frames in source) or DSTCIDX (number of bytes between frames in destination)

Figure 5: Definition of ACNT, BCNT and CCNT

The reference point for the index number depends on the synchronization type. The amount of data transferred upon reception of a trigger/synchronization event is controlled by the synchronization type chosen (by writing the SYNCDIM bit in Channel Options Parameter (OPT)). There are only two synchronization types supported: A-synchronized transfers and AB-synchronized transfers.

A-synchronized transfers

In A-synchronized transfers, an EDMA3 synchronization event initiates a transfer of the 1^st dimension of ACNT byte, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information for only one array. Thus, BCNT x CCNT events are needed in A-synchronized transfers to completely service a PaRAM set. Arrays are always separated by SRCBIDX and DSTBIDX. Frames are separated by SRCCIDX and DSTCIDX.

	For A-synchronized transfers, after the frame is exhausted, the address is updated by adding (S/D)CIDX to the beginning address of the last array in the frame. The example below is an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. SRCCIDX/DSTCIDX is the difference between the start of Frame 0 Array 3 to the start of Frame 1 Array 0. In this example a total of 12 synchronization events exhaust a PaRAM set.
 

Figure 6: A-synchronized transfers (ACNT = n, BCNT = 4, CCNT = 3)

AB-synchronized transfers

In AB-synchronized transfers, each EDMA3 sync event initiates the transfer of 2 dimensions or one frame. Each event/TR packet conveys information for one entire frame of BCNT arrays of ACNT bytes. Thus, only CCNT events are needed to completely service a PaRAM set. Arrays are always separated by SRCBIDX and DSTBIDX and frames separated by SRCCIDX and DSTCIDX. With AB-synchronized transfers, after a TR for the frame is submitted, the address is updated by adding (S/D)CIDX to the beginning address of the beginning array in the frame. This is different from A-synchronized transfers where the address is updated by adding (S/D)CIDX to the beginning address of the last array in the frame. The example below is AB-synchronized transfers of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. A total of 3 sync events (CCNT) exhaust a PaRAM set, which is equivalent to a total of three transfers of four arrays each, completes the transfer. Note that AB-synchronized transfers need lesser events than A-synchronized transfers.

Figure 7: AB-synchronized transfers (ACNT = n, BCNT = 4, CCNT = 3)

EDMA3 Transfer Controller (EDMA3TC)

Slave to the EDMA3CC, the EDMA3 Transfer Controller (EDMA3TC) is responsible for data movement. It issues read/write commands to the source and destination addresses that is programmed for a given transfer. However, the operation is transparent to the user. EDMA3TC has six transfer controllers (TC); three transfer controllers with 128 bit wide read-write ports and three 64 bit wide read-write ports. It can occupy up to four in-flight TR, as well as providing a programmable priority level. Besides that, EDMA3TC supports 2-dimensional transfers with independent indexes on source and destination. In addition, it also supports two modes of transfers: increment and FIFO. The little-endian and big-endian operations are both supported by EDMA3TC as well as interrupt and error supports. Note that MMR bit fields are fixed position in 32-bit MMR regardless of endianness. The main blocks of EDMA3TC are:

• DMA program register set: stores transfer requests received from EDMA3CC

• DMA source active register set: stores the context for DMA TR currently in progress in the read controller
• Read controller: issues read commands to the source address

• Destination FIFO register set: stores the context for DMA TR currently in the write controller

• Data FIFO: holding temporary in-flight data

• Completion interface: sends completion codes to the EDMA3CC when a transfer completes, and generates interrupts and chained events

Figure 8: EDMA3TC block diagram

Functionality

EDMA3TC starts in the idle state. Once it receives its first TR in the DMA program register set, the TR is immediately sent to the DMA source active set and the destination FIFO register set. If at the same time, EDMA3TC is pended from EDMA3CC, the second TR is loaded into the DMA program register set to ensure that it can start as soon as the active transfer is completed. Once the current active set is exhausted, the second TR is loaded from the DMA program register set into the DMA source active set and destination FIFO register set. Regarding the read controller, it issues read commands which is governed by the rules of command fragmentation and optimization. These read commands are however issued only when the data FIFO has available space for the data read. When sufficient data are in the data FIFO, the write controller starts issuing a write command, followed by the rules for command fragmentation and optimization. These commands are defined by the transfer controller default burst size (DBS), which is of 64 bytes in the TMS320C6474.

	Depending on the number of entries, the read controller can process up to two or four transfer requests ahead of the destination, depending on the amount of free data FIFO.

Initiating a Transfer Request (TR)

Initiating a transfer depends on the channel\’s type: either a DMA or a QDMA channel.

DMA

Three possibilities to initiate transfers on DMA channels:

• Event-triggered TR

A peripheral, system or externally-generated event triggers a TR. When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the event register (ER.En = 1). Upon activation of this bit, the EDMA3CC prioritizes and queues the event in the appropriate event queue. Once the event reaches the head of the queue, it is evaluated for submission as a TR to the transfer controller. If the PaRAM set is valid (not a NULL set, which is a PaRAM set with all count fields cleared except for the link field), then a transfer request packet (TRP) is submitted to the EDMA3TC and the ER.En bit is cleared so that a new event can be safely received. However, if the PaRAM is a NULL set, then no TR is submitted and ER.En bit is cleared. Simultaneously, the corresponding channel is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to a null TR. When an event is received, the corresponding event bit in the event register is set (ER.En = 1), regardless of the state of EER.En. If the event is disabled when an external event is received (ER.En = 1 and EER.En = 0), the ER.En bit remains set. If the event is subsequently enabled (EER.En = 1), then the pending event is processed by the EDMA3CC and the TR is processed/submitted, after which the ER.En bit is cleared.

If an event is being processed (whether is being prioritized or is in the event queue) and another sync event is received for the same channel prior to the original being cleared (ER.En != 0), then the second event is considered as a missed event in the event missed register (EMR.En = 1).

• Manually-triggered TR

The CPU triggers a transfer manually using manually-triggered TR mechanism. This is achieved by writing a 1 to the corresponding bit in the Event Set register(s) (ESR/ESRH) to kick-off the transfer. Once the bit is enabled, the event is being prioritized in the appropriate event queue. It is then evaluated for submission as a TR to EDMA3TC. Similar to event-triggered TR, if the PaRAM set associated with the channel is valid, then the TR is submitted to the associated EDMA3TC and the channel can be triggered again. Else, no TR is submitted. Other conditions of triggering are similar to the one in event-triggered TR.

• Chain-triggered TR

Upon completion of a transfer (or a subtransfer), another event for another channel is automatically set using chaining transfers mechanism. Once a chained completion code is detected, the value of which is written in the transfer completion code (bit TCC\[5:0\] in OPT register of the PaRAM set associated with the channel) results the activation of the corresponding bit in the chained event register (CER). As this bit is set, EDMA3CC queues the event in the appropriate event queue. When the event reaches the head of the queue, it is evaluated in a similar way as the two transfer requests explained previously.

QDMA

QDMA channels are typically used when a single event accomplishes a complete transfer since the CPU (or other EDMA3 programmers) must reprogram some portion of the QDMA PaRAM set in order to retrigger the channel. In other word, these transfers are programmed with BCNT = CCNT = 1 for A-synchronized transfers and CCNT = 1 for AB-synchronized transfers. TRs are issued when a QDMA event gets latched in the QDMA event register (QER.En = 1). Two possibilities to initiate transfers on QDMA channels:

• Auto-triggered TR

A transfer is triggered when a CPU (or any EDMA3 programmer) writes address to a PaRAM address. This address is defined as a QDMA channel trigger word (the trigger word is programmed in the QDMA channel mapping register (QCHMAPn)) for the particular QDMA channel. The QDMA channel is enabled via the QDMA event enable register (QEER.En = 1). Auto-triggering allows QDMA channels to be triggered by CPU(s) with a minimum number of linear writes to PaRAM.

• Link-triggered TR

When linking occurs, the transfer is triggered as soon as the trigger word is written to the QDMA channel PaRAM set. This transfer occurs when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel. Once the corresponding channel is enabled via the QDMA event enable register (QEER.En = 1), the EDMA3CC prioritizes the event in the appropriate event queue. It is then evaluated for submission as a TR to EDMA3TC when the event reaches the head of the queue. Link triggering allows a linked list of transfers to be executed using a single QDMA PaRAM set and multiple links PaRAM sets.

EDMA3 transfer setup, edma_setup.c

There are two functions in edma_setup.c:

1. vConfigEdma() EDMA3 configuration
2. vCloseEdma() closing EDMA3 handle

EDMA3 configuration, vConfigEdma()

/************************************
Global variable definitions
************************************/

/************************************
Local variable definitions
************************************/

  set configuration

  PaRAM set configuration

The EDMA3 module configuration begins by initializing the CSL library, CSL_edma3Init(&Edmacontext). This function initializes the context object and it needs to be invoked before using an EDMA3 module. Upon success, this function returns CSL_status CSL_SOK. The next step to accomplish is to open the EDMA3 module requested, CSL_edma3Open(). The function returns an EDMA3 handle; it is the input for the rest of the APIs used within the EDMA3 module. Once the EDMA3 handle is returned successfully, DMA/QDMA module hardware setup of the EDMA3 is accomplished by calling the function CSL_edma3HwSetup(). It also programs the channel to PaRAM mapping.

  CSL_edma3Init(&Edmacontext);

  hEdmaModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus);

  hwSetup.dmaChaSetup  = &dmahwSetup\[0\];
  hwSetup.qdmaChaSetup = &qdmahwSetup\[0\];
  CSL_edma3HwSetup(hEdmaModule, &hwSetup);

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