EDMA Background Activity for OMAP-L1x/C674x/AM1x Throughput Measurements
This page describes the EDMA background transfers that were used when collecting throughput data on OMAP-L1x/C674x/AM1x peripherals. The peripheral throughput data is presented in the Wiki article OMAP-L1x/C674x/AM1x SOC Architecture and Throughput Overview.
It is often useful to understand the maximum throughput/bandwidth a peripheral can achieve when there is no other activity in the system-on-a-chip (SOC). This maximum throughput/bandwidth allows us to quickly guage if a peripheral can meet a specific use case requirement.
However, once this initial assessment is complete, it is necessary to consider the performance of the peripheral in a real-world scenario. In a real system, it is unrealistic to assume that a peripheral will operate in a vacuum, completely unaffected by other activity in the SOC. For example, the LCD controller will compete for DDR bandwidth with the ARM cache controller, the EDMA transfer controllers, and any other masters accessing external memory.
For this reason, most of the peripheral throughput data presented in the Wiki article OMAP-L1x/C674x/AM1x SOC Architecture and Throughput Overview includes an EDMA background component that is used to simulate system activity in a real-world use case scenario. This EDMA background activity was purposely injected to get a better understanding of the impact other activity in SOC would have on peripheral throughput.
EDMA Transfer Configuration
The EDMA background activity consisted of a continuous 4K-byte EDMA transfer from external memory (either DDR2 or SDR SDRAM) to DSP L2 memory. The EDMA transfer was set up with ACNT = 4096, BCNT = CCNT = 1 and self-chaining and linking enabled. The read rate setting and default burst size (DBS) setting of the EDMA transfer controller were varied to throttle the data rate of these background transfers. The read rate setting controls the number of EDMA clock cycles between read command and the DBS setting specifies the maximum number of bytes per read command issued by the transfer controller. For example, a read rate setting of 4 with a DBS setting of 16 means that the EDMA will issue continuous 16-byte read commands spaced apart by 4 EDMA clock cycles. The read rate is specified on a per EDMA transfer controller (TC) basis through the RDRATE register. The DBS is also configurable on a per EDMA TC basis through the Chip Configuration 0 Register (CFGCHIP0).
Read Command Rate Register (RDRATE)
Chip Configuration 0 Register (CFGCHIP0)
External Memory Bandwidth Usage
The figure below shows the percentage of external memory bandwidth that was utilized by EDMA background activity for a given read rate setting and default burst size setting. The data was collected on an OMAP-L137 devices, but similar trends can be observed on other C674x and OMAP-L13x devices. Notice that external memory is close to 90% utilized with a read rate of 0 (back-to-back reads) for any given DBS setting.
% Utilization with Read Rate Variation For All DBS
- A utilization of 100% indicates a data rate of 532Mbytes/sec (133MHz x 4bytes).
- EMIF3c refers to the EMIFB on OMAP-L137 devices.