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Enabling 64x+ Cache

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Introduction

The 64x+ DSP core has a two-level cache architecture consisting of L1P, L1D, and L2 cache.

Enabling the cache

Each of the caches (L1P, L1D, L2) is independently configurable through its own configuration register (L1PCFG, L1DCFG, L2CFG respectively). These are memory mapped registers and are described in the 64x+ DSP Megamodule User's Guide.

Don't forget the MAR bits!

Perhaps the most common mistake people make with respect to enabling cache is that they forget to set the appropriate MAR bits. What is MAR? MAR stands for Memory Attribute Register. In short, there is a huge group of these registers where each register corresponds to a 16MB section of the memory map. By setting the MAR register to 1 you are telling the 64x+ core that it is allowed to cache data in the corresponding 16MB section of memory. If, for example, you did not set any of the MAR bits corresponding to your DDR, then none of the data in DDR would actually get cached! So as you can imagine, this is a very important step.

You only need to configure the MAR bits for the external memory. When it comes to the internal memory the corresponding MAR bits are already set for you (i.e. L2 SRAM can be allocated in L1D cache). Furthermore you would never want to turn them off as there is no need since data coherence is maintained by the hardware between L1D and L2.

When would you NOT want to set the MAR bits? You would want to leave a MAR bit as 0 if that corresponding memory range has some kind of memory mapped register (e.g. inside an FPGA/CPLD) or if you had attached a FIFO in that memory range.

Here's a quick tip for figuring out what memory range a MAR bit corresponds to. Since each MAR corresponds to a 16MB range of memory, that corresponds to a 24-bit address boundary. In other words, the most significant byte of the address corresponds to the MAR. For example, address 0x80000000 is often the start of DDR. Take the most significant byte, 0x80. Since 0x80 = 128, that means MAR128 controls that address range.

Configuring the cache using DSP/BIOS

Static/Graphical Configuration

You can use the graphical configuration to setup your 64x+ cache configuration. You simply go to System, right-click on Global Settings, and select Properties. Then you go to the 64PLUS tab and you'll see this dialog box:

Enabling 64xp Cache BIOS.jpg

In the above example the L1P and L1D caches are enabled with 32KB being used as cache. The L2 cache is disabled (0k) meaning that all the L2 memory will be available as SRAM. Finally, you see further down that MAR128-MAR131 are set. That signifies that 64MB of DDR2 is cacheable beginning at address 0x80000000.

Static/Text Configuration

If you're not using graphical config, but instead hand-editing your .tcf script, you can get the same effect as above with this line:

/* set MAR register to cache external memory 0x80000000-0x83FFFFFF */
bios.GBL.C64PLUSMAR128to159 = 0x0000000f;

Dynamic Configuration

If you wish to programmatically configure/reconfigure the cache at run-time you should use the BCACHE module that is part of DSP/BIOS. The BCACHE module is documented in the API guide. All the BIOS documentation is packaged together with the libaries. It can be found in the directory <bios_install_dir>/doc.

Other resources

64x+ Cache User's Guide

64x+ DSP Megamodule User's Guide, Ch. 2-4

Device data sheet to see the cache/RAM size for a specific device

Cache Management - discusses how to avoid cache coherence issues