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FAQ - C6000

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C6000 FAQ

This FAQ pertains to general issues related to C6000 devices

Q: Is it possible to use one source for EMIF clock-in at reset and then change it to another different source during run-time?

For all C6000 devices (EXCEPT C6711C/D, C6712C/D, C6713), changing EMIF input clock sources at run time is not possible. The clock source is part of the boot-word that is latched in at reset time, so changing it would require you the reset the device. For C6711C/D, C6712C/D, and C6713, it is possible to change EMIF input clock source during run-time via software programming of the DEVCFG.EKSRC bit. Users must ensure that no EMIF activities are in progress when switching clock sources.

DEVCFG(Device Configuration) allows the user to control peripheral selection. This register also offers the user control of the EMIF input clock source. The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register. For more detailed information on the device configuration register, see the Device Configurations section of this data sheet. [C6713]

Q: The load double word (LDDW) uses only one functional unit to load 2 words. Does instructions exist that will store 2 words from registers into memory at the same time, using only one functional unit?

This FAQ applies to all versions of CCS for TMS320C62x and TMS320C67x processors:
There isn't an instruction that will store double words using one functional unit. The user would need to use 2 store commands to store a double word.

Note: TMS320C64x/C64x+ processors have a STDW instruction.

The application report SPRU732 for C64x/C64x+ DSP and CPU reference guide will give more information on STDW instruction and Instruction Compatibility Between C62x, C64x, and C64x+ DSPs.

Q: Limitation of pulse mode for timer in C6X

When the pulse mode is selected for pulse generation, the PWID bit in the Timer Control Register (CTL) is used to set the pulse width. The pulse width can be set to either one or two timer input clock periods corresponding to PWID bit being equal to 0 or 1. Since the Period Register value is 1, either of these pulse widths will result in TSTAT being high always. So for period register value = 1, clock mode has to be used. TSTAT will remain high whenever Timer Period Register is less than or equal to (PWID + 1).