GSG:Connecting to slave cores in SoC devices v5

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Connecting to slave cores in SoC devices


Introduction

Most of the devices have a single core. However, in SoC devices usually one of the cores is the master (usually an ARM) and controls one or more additional cores (the slaves). In these cases it is impossible to load and debug code in the slave cores without previous intervention from the master core, which is not only responsible for releasing the slave cores from reset but can also initialize PLLs and external memory interfaces (EMIF).
This page shows how to properly connect and debug code in SoC devices.

Connecting to slave cores in SoC devices

1. Create the target configuration normally using the editor (check the section GSG:Debugging_projects). Make sure the correct GEL files are added (GSG:Adding_GEL_files_to_a_target_configuration).

Tip: in this particular case it is usually easier to find the target configuration if it is saved to a shared location instead of inside a project, but both methods work.
Tip: in CCSv5.2 and newer, a board configuration can be selected (BeagleBone, LCDKOMAPL138, etc.) instead of a plain device selection (AM3359, OMAPL138) as they already have all GEL scripts pre-configured. For details, check the Device support files page.


2. Open the target configurations view: go to menu View --> Target Configurations.

3. Right-click on the desired target and select Launch Selected Configuration.

Fig. 1 - Launching a system configuration


4. Once the debugger is launched, right-click on the master core and select Connect Target.

Fig. 2 - Connecting to the master core


5. Go to menu Scripts and select the correct slave core startup GEL script. The exact name varies between devices, but for OMAPL138 it is named DSP wakeup, for OMAP3 it is IVA22_GEM_startup, etc.

Note: some ARM GEL configurations of CCSv5 already enable the DSP at connect time, thus not requiring this step.


Fig. 3 - Releasing the slave core from reset


6. Right-click on the slave core and select Connect Target.

7. Load the program to the target by going to menu Run --> Load... --> Load Program...

Core status

The status of the cores can be inspected using the Target Status view.

1. Go to the Debug view, right-click on it and select Show All Cores

2. Expand the tree under Non Debuggable Devices, select the first core (the one which ends with IcePick_C or IcePick_D) and connect to it (Ctrl+Alt+C or menu Run --> Connect Target)

3. Go to menu View --> Other and type Target Status on the Type filter text box.

4. Select the Target Status and click OK.

5. The Target Status view will be shown. Expand the selections and check the status of all the cores of your device.

  • The processor cores will be shown under a tree of non-debuggable cores (mostly named CS_DAP_xx). These non-debuggable cores must be connected to expose the status of the processor core.
  • A core that is ready to be connected will be shown as Clk On, Power On, CLK Down inactive, Power Down inactive, Not In Reset, Reset (None)
  • A core that is not ready to be connected will be shown as Clk Off, Power Off, CLK Down inactive, Power Down inactive, In Reset, Reset (None)
  • A core that is deliberately powered down will be shown as Clk Off, Power Off, CLK Down active, Power Down active, In Reset, Reset (None)


Additional Topics

Now that you have finished learning about Connecting to slave cores in SoC devices, you can check other Advanced Topics of the CCSv5 Getting Started Guide.