General hardware design/BGA PCB design

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BGA PCB Design Main Page

This page is designed to help customers understand what's involved with PCB design for BGAs.  There is a "definitions" section at the end of this page for those who may not know all the terms used here.

For the special page on 0.65mm pitch routing, click below.

BGA Ball Pad Size

One of the most common questions we get is about what ball pad size to use.  Optimal BGA ball pad size is easily found by referencing the IPC.org specifications for ball pad sizing.  The IPC is an organization that is made up of hundreds of PCB manufacturers and assemblers worldwide working together to determine the optimal specifications for high PCB yield and reliability including BGA ball pads.


The IPC has a specification called IPC-7351A.  This specification provides recommendations for all known BGA ball sizes.  Referencing this table will show the optimal ball pad size for any BGA design:


IPC-7351A for NSMD Pads

Nominal

Ball

Diameter*

Reduction

Land

Pattern

Density Level

Nominal

Land

Diameter

Land

Variation

0.75
25%
A
0.55
0.60-0.50
0.65
25%
A
0.50
0.55-0.45
0.6
25%
A
0.45
0.50-0.40
0.55
25%
A
0.40
0.45-0.35
0.5
20%
B
0.40
0.45-0.35
0.45
20%
B
0.35
0.40-0.30
0.4
20%
B
0.30
0.35-0.25
0.35
20%
B
0.30
0.35-0.25
0.3
20%
B
0.25
0.25-0.20
0.25
20%
B
0.20
0.20-0.17
0.2
15%
C
0.17
0.20-0.14
0.17
15%
C
0.15
0.18-0.12
0.15
15%
C
0.13
0.15-0.10
  • Can be found on the TI Mechanical package drawing available in the TI product folder.

This table is very handy.  If someone wanted to look up the correct pad size for a 0.8mm pitch BGA, they can look at the mechanical diagram for that package to determine the ball size.  For most embedded procesor 0.8mm pitch BGAs, the ball size is 0.5mm.  Find 0.5mm on the left hand column and follow that to the column that says "Nominal Land Diameter" and see that the recommendation for the ball pad is 0.4mm. 


The far left column shows acceptable manufacturing variances, not allowable design targets (all manufacturing has tolerances), so please use the "Nominal Land Diameter" column to determine the correct BGA ball pad design target size.



PCB Routing Methods

Types of arrays:

For embedded processors, TI makes two types of BGAs

1.  Standard BGA arrays.  These are characterized by the standard footprint which is usually either a full array (fully populated), or an array with a "moat" (a square of depopulated balls in the array that separates the inner array, which is mostly power and ground balls, with the outer array of signals).

2.  Via Channel(TM) arrays.  These are BGA arrays that have sections of depopulated balls and when viewed from a distance look like an explosion, or snowflake pattern.  These arrays are specifically designed to reduce PCB cost by allowing large PCB feature sizes and reduced PCB layers.  If a part uses a Via Channel BGA array, it is mentioned on the bulleted list on the first few pages of the part data sheet and there should be a PCB layout application note like the OMAP 3530 note at the end of this page.  Only TI makes Via Channel parts. 


What is Via Channel(TM)?

Via Channel is a new TI feature specifically designed to reduce PCB manufacturing cost by placing the BGA balls in patterns specifically designed for optimal via and trace placement. 

This feature uses a special BGA array design to allow two major advantages:

- Large PCB feature sizes (regardless of ball pitch)

- Reduced PCB layer count (because of the increased layer efficiency)


Currently there are five main embedded processor product lines with a Via Channel package, and more are on the way.

Via Channel BGA arrays are designed to use standard PCB processes (no micro vias or HDI required) regardless of ball pitch, and they have much reduced PCB layer requirements.  All current Via Channel designs can be done in 4 total PCB layers (see the Via Channel PCB layer section below).


To learn more about this unique design feature, here's a short slide set to explain graphically how Via Channel works:


PCB Feature Sizes For Standard BGAs

Standard arrays are fairly easy to estimate PCB feature sizes and layers for.  These figures can be arrived at with a calculator, however be careful to make sure a line of the specified width can be used in between vias of the specified width.  Just because an 16 mil via can be used on a 0.65mm pitch part does not mean it's possible to route a 4 mil trace in between the vias.

PCB Typical Feature Sizes For Standard (non-Via Channel) BGA Arrays
Ball Pitch Via Diameter

Via Hole

Size

Trace Size Clearance

Micro

Vias?

0.8mm pitch

18 mil

10-8 mil

4-5 mil

4 mil

No
0.65mm pitch

16 mil*

12 mil

8 mil*

6 mil

4 mil*

4 mil

4 mil*

4 mil

No

Yes

0.5mm pitch 10 mil 5 mil 3 mil 3 mil Yes
0.4mm pitch 10-8 mil 5-4 mil 3 mil 3 mil Yes
  • 16 mil diameter/8 mil hole vias are only possible if done in a creative way that puts traces only in between every other via.  In other words, 16/8 vias, when placed between the balls, will move enough to allow one 4 mil trace per pair, but not one 4 mil trace per via, so for some designs like the DM365 and DM355, 16/8 mil vias should be possible in your application since there are some areas to place vias in the array.  However for Freon, since it's a full array, it is not possible to use 16/8 vias unless only every other pin is used (not likely).  16/8 vias are uncommon in the PCB fab world, but some companies can do them without micro vias.


PCB Layer Count For Standard BGAs

The layers required to route a particular design can be easily estimated once the signals and location of those signals has been highlighted.

Assuming that the above required PCB feature sizes for that pitch are used, the PCB layers will be used as follows:

The first 2 rows will route on the top layer

The second 2 rows will route on the second layer

An additional PCB layer will be required for every row in past the first 4.

So, if "Rows_in" = the maximum number of rows in (from the outside of the BGA array) the centermost signal is located, then:

2 Rows_in = 1 PCB signal layer

3 Rows_in = 2 PCB signal layers

4 Rows_in = 2 PCB signal layers

5 Rows_in = 3 PCB signal layers

6 Rows_in = 4 PCB signal layers

7 Rows_in = 5 PCB signal layers


So if a signal called I2C_CLK was required in the design, and it was located five rows in from the outside (counting all rows), then it would require 3 PCB signal layers, plus at least 2 PCB layers for power and ground, so that's 5 PCB layers total, which makes a 6 layer board (it doesn't make sense to build an odd layer board).

PCB Feature sizes for Via Channel(TM) BGAs

If the part used is a Via Channel(TM) part, it has been specifically designed to reduce PCB costs.  The PCB feature sizes are now independant of the ball pitch since the vias no longer have to be placed in between four balls.  Via Channel also routes more signals out on lower layers.  Where standard array trace density on lower PCB layers is limited by via interference of the traces, Via Channel designs are mostly free of this restriction, so more traces can be routed on lower layers thereby reducing the number of PCB layers required.  Most Via Channel designs are designed for a four layer PCB (minimum).

 

PCB Typical Feature Sizes For Via Channel BGA Arrays
Ball Pitch Via Diameter

Via Hole

Size

Trace Size Clearance

Micro

Vias?

0.8mm pitch

20 mil

18 mil

12-10 mil

10-8 mil

5 mil

4 mil

5 mil

4 mil

No
0.65mm pitch

20 mil

18 mill

12-10 mil

10-8 mil

4 mil

4 mil

4 mil

4 mil

No

No

0.5mm pitch 18 mil 10 mil 4 mil 4 mil No


PCB Layer Count For Via Channel(TM) BGAs

Via Channel BGAs are specifically designed to require only 4 total PCB layers.  Depending on the power requirements and the power signal routing, an additional power layer may be required bringing the PCB layers to 6, but with very careful design this should be able to be avoided.


BGA Decoupling (Bypass) Capacitor Selection and Placement

BGA Decoupling Capacitor Selection and Placement


Other good BGA Information

Some good TI application notes on BGAs:

More to come


Suggested BGA Solder Temperature Profile

under construction


BGA PCB feature definitions (for the purposes of this page)

  • Ball pads - Also known as BGA "lands". This is the copper that the BGA ball solders to.
  • NSMD pad - Non-Solder Mask Defined ball pad. This kind of pad has an opening that is defined only by the size of the ball pad. The solder mask is applied around the ball pad and does not cover it. This kind of pad is more popular lately and has the advantage of increased ball adhesion because the ball flows around the sides of the ball pad and grips on the top and the sides. This kind of pad is usually recommended for BGA designs 0.5mm and above.
  • SMD pad - Solder Mask Defined ball pad. This kind of pad has a large copper area, but the solder mask covers the edges, so the opening is known as solder mask defined. This kind of pad is sometimes best for very small pitch pads where ball shorting is an issue.
  • Via diameter - the full width of the via annular ring
  • Micro via - a via that is laser drilled.
  • HDI - High Density Interconnect. This is the type of board that uses very small vias like micro vias. When a board uses micro vias it is called an HDI board.

Conversion between mm and mils

• 0.075mm = 3 mils (0.003”)
• 0.1mm = 4 mils (0.004”)
• 0.125mm = 5 mils (0.005”)
• 0.2mm = 8 mils (0.008”)
• 0.4mm = 16 mils (0.016”)
• 0.45mm = 18 mils (0.018”)
• 0.5mm = 20 mils (0.020”)