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Hardware Design Checklist
As you are creating the schematics for your project here are a few things to consider.
- 1 Before you begin
- 2 Critical Connections
- 3 Peripherals
- 4 Debug Considerations
- 5 Other
- 6 References
Before you begin
Make sure you have the latest version of documentation, especially the data sheet and silicon errata.
TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important.
TIP: - on each ti.com device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata.
- Have you verified that your pin labels correspond to the correct pin numbers?
- Have you verified that the power pins are connected to the correct supply rails?
- Internal pull-up/pull-down resistors are implemented with weak transistors. As the voltage present on the I/O pin varies the relative gate voltage to this weak transistor changes which will cause the effective pull-up/pull-down resistance to change. Therefore, internal resistors do not have a linear response like external resistors. The non-linearity along with process voltage and temperature variations require internal pull-up/pull-down resistors to be specified with a wide range of resistance or current sourcing/sinking.
- The input current without a pull-up or pull-down turned on defines the input leakage without any current from internal pull resistors. The input current with a pull-up or pull-down turned on defines a combination of input leakage current and current required to force the internal pull resistors to the opposite voltage rail. For example, if an internal pull-up is turned on the value shown represents the total current required to pull the input to VSS.
- When deciding what value of external resistor to use, you must consider the worst case combination of all internal leakage paths of all devices connected to a signal and make sure the external resistor is able to force these internal leakage paths to a potential greater than Vih min, or less than Vil max.
Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling.
PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply.
Are all requirements being met in terms of the order, delays, etc. of the power supplies?
Make sure your input clock/crystal meets the data sheet requirements. For example:
- ESR for crystal
- Load capacitance meets both the crystal’s and processor’s requirements
- Crystal and caps placed physically close to processor
- Double check proper voltage level for clock (some devices will use core voltage, others I/O voltage).
- If there are any PLL configuration pins make sure they are set such that the resulting frequency is within device spec. Also, having alternate population options for those PLL pins could be handy.
OSC Internal Oscillator Clock source
The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components.
- OSC Crystal Circuit Schematics
In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality:
Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms
However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs.
Please refer the below application note for calculation of Rs and RBais values:
Please refer the application note for the calculation of Rs and RBais values Crystek Application notes
Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the OMAPL1x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.
Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable!
A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets.
Also, you might want to have a reset button on your board as it can be helpful for development.
- Double check that the boot configuration pins are set to the correct option.
- It's highly recommended to have some population options to be able to easily change the reset mode. This can be handy in a variety of circumstances. For example, if you were doing a NOR flash boot and you ever accidentally put in some bad code you might end up in a scenario where you can't connect to the device with emulator because it's in a bad state, and you can't reprogram the flash as a result! Having an alternate boot mode can be a life saver!
- Read carefully the initialization section in the Technical Reference Manual of your processor. We may have to deal with important information that can change your design. Look for which chip select is used by default, default clock setups, bus widths, wait states, supported booting devices, initial fetch address and interrupt vector addresses, default memory map and so on.
- CAUTION: Be careful if anything is hooked up to these pins (i.e. if the pins are have multiple uses such as GPIO or other peripherals). You must make sure that the boot pins are at the proper levels when power-on reset occurs such that the correct values are latched in order for the device to boot correctly!
Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately.
- Check that there are no unnecessary USB_DM or USB_DP connections that would form stubs.
- Check that there is nothing on the DP/DM lines (except for possibly a USB 2.0 certified surge suppressor)
- USB supports hot insertion and removal so it is very vulnerable to ESD resulting from this. External ESD protection like the TPD2E001 or TPD3E001 is recommended. For USB OTG the recommended ESD protection is the TPD4S012. Any USB 2.0 certified ESD protection chip is acceptable as long as the USB PCB routing guidelines are followed.
DDR2 Routing Checklist
External Memory Interface (NOR/async)
The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly.
- ~5K pull ups on both lines (only one set, or two sets of 10K pull ups) are recommended
- Make sure all devices on a given I2C bus have unique addresses (often this is configurable through a pin to enable multiple of the same device)
This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:
- TX ---> RX
- RX <--- TX
This is something often done incorrectly which can severely impact your ability to develop code!
- Please follow these recommendations when designing your JTAG interface.
- The XDS Connector Design Checklist provides a convenient list of recommendations per XDS/JTAG signal.
- You might also want to look at the article JTAG Connectors when deciding which header to put on the board. Double-check the pin-out!
For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well.
Voltage Level Changes
Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later.
Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction.
For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption.
The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools.
The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board.
This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.