How to program VPBE YCC8 digital out

From Texas Instruments Embedded Processors Wiki

YCC8 mode require nonstandard timing

• Set VMOD.VMD = 1
• Set HINTVL and HVALID twice the size of intended resolution
• Set VINTVL and VVALID to the correct resolution
• Set OSDCLK0=1 OSDCLK1=2 (divide internal DCLK by half)
• Set OSD window to match display resolution
• VENC.DCLKCTL and VENC.DCLKPTNx will only need to be programmed if LCD module expect different clock rate or latch data on both clock edges.

Note: On the OSD vs. VENC resolution setting, user should be able to program video window to actual resolution in the OSD, but as “twice the width” on the VENC. The reason for this is that the OSD keep track of the picture dimension/location/etc., whereas the VENC takes care (almost independently) of the physical interface. As long as the OSD picture fits in our valid region, the VENC should be able to insert the data in the right place

Example:  (Register setting for 720x489 resolution in YCC 8 bit mode)

/* VENC Registers */
VENC_0_REGS->VIOCTL = 0x6000;
VENC_0_REGS->SYNCCTL = 0x3;
VENC_0_REGS->LCDOUT = 0x1;
VENC_0_REGS->VINTVL = 0x1E0;
VENC_0_REGS->HINTVL = 0x5D2;
VENC_0_REGS->HSTART = 0x30;
VENC_0_REGS->VSTART = 0x0;
VENC_0_REGS->VSPLS = 0x1;
VENC_0_REGS->HSPLS = 0x1;
VENC_0_REGS->VVALID = 0x1E0;
VENC_0_REGS->HVALID = 0x5A0;
VENC_0_REGS->DCLKCTL = 0x8A00;
VENC_0_REGS->DCLKPTN0 = 0x1;
VENC_0_REGS->DCLKPTN1 = 0x0;
VENC_0_REGS->DCLKPTN2 = 0x0;
VENC_0_REGS->DCLKPTN3 = 0x0;
VENC_0_REGS->DCLKPTN0A = 0x2;
VENC_0_REGS->DCLKPTN1A = 0x0;
VENC_0_REGS->DCLKPTN2A = 0x0;
VENC_0_REGS->DCLKPTN3A = 0x0;
VENC_0_REGS->DCLKHSTT = 0x0;
VENC_0_REGS->DCLKHSTTA = 0x1;
VENC_0_REGS->DACTST = 0xF000;
VENC_0_REGS->OSDCLK0 = 0x1;
VENC_0_REGS->OSDCLK1 = 0x2;
VENC_0_REGS->CLKCTL = 0x111;

 

/* OSD Registers */
OSD_0_REGS->VIDWINADH = 0x2A; /* SDRAM start address higher 7 bits */
OSD_0_REGS->VIDWIN0ADL = 0x0; /* SDRAM start address lower 16 bits */
OSD_0_REGS->VBNDRY = 0x8; /* Increment mode of address counetr */
OSD_0_REGS->VIDWIN0OFST = (0x8 << 9) | (0x2D); /* SDRAM start adress and offset burst size*/
OSD_0_REGS->VIDWIN0XL = 0x2D0;
OSD_0_REGS->VIDWIN0YL = 0x1E0;
OSD_0_REGS->BASEPX = 0x7A;
OSD_0_REGS->BASEPY = 0x12;
OSD_0_REGS->MISCCTL = 0x10;
OSD_0_REGS->OSDWINADH = 0x0E0E; /* SDRAM start address higher 7 bits */
OSD_0_REGS->OSDWIN0ADL = 0x0; /* SDRAM start address lower 16 bits */
OSD_0_REGS->VBNDRY = 0x8; /* Increment mode of address counetr */
OSD_0_REGS->OSDWIN0OFST = (0x8 << 9) | (0x14); /* SDRAM start adress and offset burst size*/
OSD_0_REGS->OSDWIN0XL = 0x140;
OSD_0_REGS->OSDWIN0YL = 0xF0;
OSD_0_REGS->OSDWIN0XP = 0x32;
OSD_0_REGS->OSDWIN0YP = 0x32;
OSD_0_REGS->MODE = 0x0100;

 

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