Implementing SMBus using USCI

From Texas Instruments Wiki
Jump to: navigation, search

SMBus Overview

The System Management Bus (SMBus) is an I2C based protocol that requires at least 2 lines (SDA, SCL) but specifies 2 optional signals (SMBALERT#, SMBSUS#). SMBus is most often found in applications that conform to the Smart Battery System (SBS) specification, but is not restricted to these systems. However, some SMBus device addresses are reserved for parts of an SBS.

SMBus vs. I2C

Unlike I2C, SMBus has a minimum bus frequency of 10kHz as well as a timeout conditions. SMBus defines a block transaction between devices and limits the transaction to 32 bytes of data. Also, SMBus v1.1 specifies an optional Packet Error Checking (PEC) feature to the read/write byte, word, and block commands. If PEC is implemented, a CRC-8 is calculated on all bytes of the transaction (not including start, stop, ACK, NACK, or repeated start bits) and added to the end of the transaction.

Since SMBus is designed for managing battery-powered systems, it follows that the specifications would constrain the I2C DC requirements to minimize the bus' power consumption. There are several other minor differences between SMBus and I2C which can be found in Appendix B of the SMBus v2.0 specification.

SMBus on the MSP430

There is an existing application note on how to implement the SMBus using the USART peripheral, which is a hardware I2C engine.

The 3xx and 5xx families of MSP430 devices have the USCI (Universal Serial Communication Interface) peripheral which is also a hardware I2C engine that can be combined with a timer to implement the SMBus protocol.

The zip file ( includes several examples of using the USCI module to implement the SMBus protocol. Even the code is written for an MSP430F5438 master AND slave, it was geared towards using a MSP430 master and a single TI battery management (BQ) slave. All of these files were created with a 100 pin MSP430F5438 + target board and CCE v3.1. The USCI B1 engine takes care of the I2C protocol and Timer 1 provides for the timeout counter. The USCI B1 uses the SMCLK divided by 10 to get ~100kHz as the SCL.

  • There are several files that will have a 430 slave cause a timeout condition by delaying the fill of the TX buffer (a 430 slave will clock stretch if it's in transmit mode and the TX buffer is empty). To cause a NACK error, simply disconnect the data line from the slave. To cause a bad data error, in the slave code, change the value of the data to be loaded into the TX buffer. If a NACK occurs or the master RX bytes that are not the values expected, then the LED will blink slowly. If a timeout occurs, the LED will blink quickly. If the transaction is successful, the LED will turn on and remain on.
  • SMBus_Mst_wiki1.c: This example performs a single "read word" command without PEC. The 430 master TX 1 byte (value: 5), sends a repeated start and then goes into reciever mode expecting 2 bytes (values 6 & 7). Use with SMBus_Slv_wiki1.c for a successful transaction, and SMBus_Slv_wikiR1.c to see a timeout condition.
  • SMBus_Mst_wiki2.c: This example performs a single "read byte" command without PEC. The 430 master TX 1 byte (value: 5), sends a repeated start, and expects 1 byte (value 6). Use with SMBus_Slv_wiki1.c for a successful transaction, and SMBus_Slv_wikiR2.c to see a timeout condition.
  • SMBus_Mst_wiki3.c: This example performs a "write block" command without PEC. The master TX 4 bytes to the slave. With a write block the data sent begins with the SMBus command code, followed by the number of bytes, n, to be sent (1<=n<=32), followed by the data. This example is easily modifiable into a "write byte/word" command. Use this with SMBus_Slv_wiki1.c for a successful transaction, and SMBus_Slv_wikiR3.c to see a timeout condition.
  • SMBus_Mst_wiki4.c: This example performs a "read word" command with PEC. The 430 master TX 1 byte (value: 5), and expects 3 bytes to be RX, (values: 4, 6, 0x66) the last one being the PEC of the transaction. 0x66 is the CRC-8 calculated on "0x91, 0x05, 0x90, 0x04, 0x06". 0x91 and 0x90 are the slave address (0x48) shifted left 1 bit and the appropriate value of the R/W bit. Use this with SMBus_Slv_wiki4.c

Feel free to use and modify the above examples, but please change the revision number if you decide to re-upload the files.