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Introduction to uPP

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This topic describes the basic features and operation of the universal parallel port, or uPP. For more detailed information about the uPP peripheral, see the Universal Parallel Port User Guide.

Overview

The uPP peripheral is a new addition to certain devices with the C674x DSP core: C6746, C6748, and OMAP-L138. It offers a high-speed parallel data bus with several important features:

  • Two independent channels with separate data buses
    • Channels can operate in same or opposing directions simultaneously
  • I/O speeds up to 75 MHz with 8-16 bit data width per channel
  • Internal DMA – leaves CPU EDMA free
  • Simple protocol with few control pins (configurable: 2-4 per channel)
  • Single and double data rates (use one or both edges of clock signal)
    • Double data rate imposes a maximum clock speed of 37.5 MHz
  • Multiple data packing formats for 9-15 bit data widths
  • Data interleave mode (single channel only)

All of these features are described in detail by the Universal Parallel Port User Guide.

Simplified Block Diagram

Upp block simple.PNG

Comparison with Other Peripherals

Unlike SPI, UART, and other serial peripherals, uPP features a parallel data bus. This fact, combined with a maximum clock speed of 75 MHz, makes uPP transfers very fast compared to some peripherals. (For instance, a single uPP channel operating at 50 MHz is as much as 16 times faster than a SPI peripheral operating at the same clock speed.)

Like HPI, the uPP peripheral is a high-speed parallel data bus. Unlike HPI, uPP requires I/O transfers to be queued by device software; it does not grant direct memory access to an external device. Additionally, uPP is considerably faster than HPI (more on this later) and has a considerably simpler protocol.

The video port is sometimes "tricked" into sending and receiving arbitrary data at high speeds. The uPP peripheral allows comparable if not superior speed to the video port. The key advantage of uPP is that it does not require data to be massaged into and out of false video frames. Also, uPP is more flexible in that its two data buses may be configured to operate in either direction. They may also be operated in the same direction simultaneously.

Signal Descriptions

Each uPP channel has four control pins in addition to its data bus. These signals implement the uPP protocol, which is designed for simplicity and to interface readily with high-speed analog-to digital converters (ADCs) and digital-to-analog converters (DACs).

Signal Description
ENABLE Driven by transmitter. Asserts while data bus is active
START Driven by transmitter. Asserts at start of DMA line(s)
WAIT Driven by receiver. Asserts to request a pause in the current transfer
CLOCK Driven by transmitter

Example Signal Diagrams

Transmit Mode

Upp transmit sig.PNG

Receive Mode

Upp receive sig.PNG

Sample Use Cases

Connection to ADC or DAC

  1. Connect to high-speed data converters (DAC, ADC)
  2. EVM add-on card features 10-bit DAC (shown) and ADC

Upp dac connection.PNG

High-Speed Data Transfer to FPGA or External uPP

  1. Connect to FPGA or another uPP-equipped DSP for high-speed digital data transfer

Upp fpga connection.PNG

Internal DMA Concepts

The uPP peripheral features an internal DMA controller that services uPP transfers without consuming system EDMA resources. The uPP DMA is based on the standard 2D model. Each transfer consists of the following parameters:

  • Window Address - A pointer to the first data word in the buffer
  • Line Size - The number of bytes per data line
  • Line Count - The number of data lines in the entire transfer
  • Line Offset - The offset address between the start of each data line

These parameters allow some flexibility in organizing uPP data buffers.

  1. The simplest case is a single line transfer, in which all of the data resides in a contiguous buffer with size equal to the line size parameter. Then, Line count is set to one (1) and the line offset is irrelevant.
  2. To generate interrupt events within the transfer of a contiguous buffer, split it into multiple lines. In this case, be sure to set the line offset equal to the line size.
  3. To repeatedly send a data buffer with minimal overhead, set the line count to an arbitrarily high number and set the line offset to zero (0). This will cause a single line to be transferred repeatedly.

uPP Interrupts

All uPP peripheral interrupt events are tied to the internal DMA controller. There are five interrupt events per channel. Each event may be separately enabled or disabled.

  • End of Window - This event occurs when a transfer completes. This will only occur once per DMA transfer.
  • End of Line - This event occurs at the end of each line within a transfer.
  • Underrun/Overflow, Internal Error, and DMA Programming Error - These events indicate various error conditions

Throughput Estimates

The following table provides throughput estimates and compares theoretical numbers with more realistic numbers derived through preliminary experimentation.

Mode Theoretical (MB/s) Realistic (MB/s)
1 Ch, 8-bit 75 60
1 Ch, 16-bit 150 120
2 Ch, 1 Way, 8-bit 150 120
2 Ch, 1 Way, 16-bit(*) 200 160
2 Ch, 2 Way, 8-bit 150 120
2 Ch, 2 Way, 16-bit 300 240
HPI (16-bit) -- 50

Note: The uPP peripheral supports a maximum clock of 50 MHz in the configuration marked with (*).

See Also

Using the uPP DSP/BIOS Driver

Universal Parallel Port User Guide

uPP Introduction Video (requires registration on my.ti.com)