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K2Ex Hardware Design Guide
- 1 Hardware Design Timeline
- 2 Introduction
- 3 Constructing the Block Diagram
- 4 Selecting the Boot Mode
- 5 Confirming Electrical and Timing Compatibility
- 6 Designing the Power Subsystem
- 7 Designing the Clocking Subsystem
- 8 Floorplanning the PCB
- 9 Creating the Schematics
- 10 Layout the PCB
- 11 Testing/Debugging
Hardware Design Timeline
Welcome to the K2Ex Hardware Design Guide. The purpose of this guide is to walk hardware designers through the various stages of designing a board around K2Ex device. The guide follows the structure shown in the Hardware Design Timeline above. Each design stage in the Timeline links to a collection of useful documentation, application notes, and design recommendations pertaining to that stage. Using this Guide, hardware designers can efficiently locate the resources they need at every step in the board design flow.
Constructing the Block Diagram
The first step in designing the hardware platform is to create a detailed block diagram. The block diagram should contain all major system ICs and illustrate which I/O ports are used for device interconnection. Below is a collection of resources to aid in the Block Diagram creation process.
- The summary of K2Ex devices architecture are available in the below link.
- The link to the K2Ex products folder provides block diagrams, application notes, tools, software, design considerations, and other related information for various products under category "Related End Equipments".
- The K2Ex EVM is a good resource for design with K2Ex devices. The EVM resource files are available under this link.
Selecting the Boot Mode
The block diagram should also indicate which interface will be used for booting this device.
- These devices contain an on-chip ROM Bootloader.
- The boot config pins are sampled at power-on-reset.
- Sets up system for boot depending on boot configuration selected.
- Depending on boot mode, copies image to internal RAM and then executes it.
- Maximum size of the boot image is 256KBytes.
- The following boot modes are supported:
- ARM I2C
- ARM SPI
- ARM EMIF
- ARM NAND
- ARM Ethernet
- ARM PCIe
- ARM HyperLink
- ARM UART
- DSP No-Boot
- Read K2Ex device data manual "Device Boot and Configuration" to understand details on different boot modes.
- See the below information for various bootloader support on K2Ex devices.
- Intermediate Boot Loader (IBL) provides the functionality of downloading the ROM file system image to the device's shared external memory (DDR). The configuration parameters for IBL are programmed into the I2C EEPROM of the target platform.The details about intermediate bootloader (IBL) are available in the below link.
- The MAD utility tool is used to build a combined boot image that can boot all cores. MAD infrastructure provides a set of utilities to help achieve the needs. The various utilities are explained in the below user guide.
Confirming Electrical and Timing Compatibility
A key step in the hardware design before beginning schematic capture is to confirm both DC and AC electrical compatibility between this device and the other ICs connected to it.
- The device data manual has important information with regards to timing and electrical characteristics.
- For High Speed Interfaces you can run IBIS simulations using IBIS models provided for K2Ex FCBGA (ABD) package to confirm signal Integrity.
- See the below information on how to use IBIS model for timing analysis.
- Those who want to have access to SERDES IBIS-AMI models and documentation must be individually approved.
- SERDES IBIS-AMI Model Request: Planned
- Note: TI provides PCB layout specifications for the following interfaces, eliminating the need to perform electrical analysis.
Designing the Power Subsystem
Once the block diagram has been validated for pin multiplexing, electrical, and timing compatibility, the power sub-system can be designed. See the below resources on estimating power consumption and designing a matching power subsystem.
- The K2E Power Consumption Summary discusses the power consumption for common system application usage scenarios for the K2Ex devices. Power consumption is highly dependent on the individual user’s application; however, this document focuses on providing several K2Ex application-usage case scenarios and the environment settings that were used to perform such power measurements.
- The K2E power estimation tool provides users the ability to gain insight in to the power consumption of the K2Ex processor. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce overall power consumption.
- For TI power management solutions, please refer TI Power Management Solutions.
Designing the Clocking Subsystem
In addition to the power subsystem, the clocking subsystem needs to be designed to provide appropriate clocks to number of internal PLLs that are used to generate the clocks within the part. These include PLLs for generating system clocks and PLLs for the high speed SerDes interfaces. These clocks can be created by clock generators and clock distribution components to drive a common clock source to multiple clock inputs on K2Ex devices.
- The K2Ex device do not allow single-ended clock input sources. Differential clock sources provide better noise immunity and signal integrity, and are required by K2Ex device.
- TI recommends below clock sources which eliminates the need for external buffers, level translators, external jitter cleaners, or multiple oscillators.
- CDCM6208 - Single PLL, 8 Differential Output Clock Tree with 4 Fractional Dividers
- CDCE62005 - Single PLL, 5 Differential Output Clock Tree with Jitter Cleaner
- CDCE62002 - Single PLL, 2 Differential Output Clock Tree with Jitter Cleaner
- CDCE62005 - Five Output Low Jitter Clock Tree with Jitter Cleaner
- For more details, please refer to the clocking sections of the device data manual and Hardware Design Guide.
- The PLL Clocking Spreadsheet in the below link will be helpful to set the internal PLL subsystem.
- K2E Clocking Spreadsheet: Coming Soon
Floorplanning the PCB
Before beginning schematic capture, it is recommended to floorplan the system PCB to determine the interconnect distances between the various system ICs.
- The thermal analysis plays a vital role in the PCB floorplan as it determines the required airflow into the PCB. The interconnect component placement may be finalized based on this analysis. Refer below links for available resources.
Creating the Schematics
At this point in the design, it is time to start capturing the schematics. See the below collection of information to aid you in creating the schematics.
- Don’t forget to install a JTAG connection for debug purpose.
- It is often helpful to refer the reference schematics throughout the schematic capture process.
- See the below reference designs for power management.
- Refer hardware design guide for specific recommendations on sections like power, clock and all interfaces
- Make sure to use the schematics checklist in the following link to validate your design.
- For detailed information on DDR3 design, see the below information.
- Plan to have an internal schematic review to go through the schematic checklist and inspect other key areas of the schematic to look for inaccuracies, missing net connections, etc.
Below are Symbol, Footprint, and Simulation Models to aid in the design of the device placement and interconnects:
- OrCad Schematic Symbol
- Allegro PCB Footprint can be extracted from EVM design file.
- 66AK2Ex BSDL Simulation Model
- AM5K2Ex BSDL Simulation Model
- 66AK2Ex IBIS Simulation Model
- AM5K2Ex IBIS Simulation Model
General hardware design information:
- BGA PCB Design
- For selecting and placing decoupling capacitors in a BGA design.
Layout the PCB
After completing schematic capture, see the below information on layout the PCB:
- It is often helpful to refer to an example layout when designing a custom PCB.
- Make sure to follow the Layout Specifications for the following Critical Interfaces:
- Plan to have an internal PCB layout review with your design team to verify that net connection traces and the power distribution network were created correctly.
- General Information Articles:
Once your custom PCB has been produced and assembled, refer to the below information for board bring-up and debugging the system.
- See the below GEL File that aid in configuring your design during debug/development.
- K2Ex Debug GEL File: This can be used with CCS to print out useful debug information such as silicon revision, bootloader error messages, current PC and PSC states, and more.
- See the below information on using the debugging Tools to debug the processor.
- Below is a collection of information on using the TI provided Booting Tools for the processor.
- Below is a link to the processor BSDL Files for verifying PCB connectivity.
- IDE: Code Composer Studio V5, Code Composer Studio V6
Refer the below information for hardware debugging.
- We recommend hardware debugging using the GEL file.
- Check the latest device Errata for your silicon revision for a matching problem description.
- The peripheral user guides are available in the below link.
- The hardware design guide for K2Ex devices is available in the below link.
- The PLL Clocking Spreadsheet in the below link to verify the clocking.
- The schematics checklist in the following link to validate the design.
- Overview of Debug and Trace Tools
- Trace technology is an important means for debugging and optimizing application codes, Trace for Profiling.
DDR debugging needs to use the GEL file and the following 2 resources - after all routing rules as defined in the DDR3 layout guide have been verified. Most issues with DDR3 come from incorrect software settings and initialization. Double check your settings with the DDR3 timing spreadsheet and initialization guide.
Once the software settings are confirmed, the layout itself may be at fault.
- Double check your layout against the routing rules in the DDR3 design requirement document.
- The most common layout problem that affects DDR3 functionality is incorrect stackup. Verify that each DDR routing layer has an adjacent solid ground plane underneath with no cuts.
- Use maximum values for the timing parameters to increase timing margins.
- Slow down the DDR3 clock to determine if it is limited to a high speed issue.