From Texas Instruments Embedded Processors Wiki

C6670 - Communication Optimized	C6671, C6672, C6674, C6678 - General Purpose
TMS320C6670 Useful Links for the C6670: Product Folder Training E2E Forum	TMS320C6678 Useful Links for the C6678: Product Folder Training E2E Forum
Next Generation C66x CorePac 4 C66x Cores @ 1.0 GHz - 1.2 GHz	Next Generation C66x CorePac Upto 8 C66x Cores @ 1.0 GHz - 1.5 GHz (1.5 GHz for two devices only) Available Options: 1, 2, 4 and 8 Core Devices
Memory Architecture 4 MB Local L2/Core (1 MB per core) 2 MB Multicore Shared Memory	Memory Architecture 4 MB Local L2/Core (512 KB per core) 4 MB Multicore Shared Memory
Peripherals & Switch Fabric RapidIO, OBSAI/CPRI, SGMII, PCIe, UART, SPI, DDR3 FFTc, VCP2, TCP3e, TCP3d, Packet & Security Accelerators HyperLink, TeraNet	Peripherals & Switch Fabric RapidIO, TSIP, SGMII, PCIe, UART, SPI, DDR3, EMIF16 Packet & Security Accelerator HyperLink, TeraNet
Accelerators FFTc, VCP2, TCP3e, TCP3d, Packet & Security Accelerators	Accelerators Packet & Security Accelerator

C6654, C6655, C6657
TMS320C665x Useful Links for the C665x: Product Folder Training E2E Forum
Next Generation C66x CorePac Up to 2 C66x Cores @ 850MHz - 1.25 GHz Available in 1 and 2 Core Models
Memory Architecture 1-3 MB Local L2 1 MB Multicore Shared Memory (C6655/57 only)
Peripherals & Switch Fabric RapidIO and Hyperlink (C6655/57 only) SGMII, PCIe, McBSP, UART, SPI, I2C, UPP, 32 bit DDR3, EMIF15 Teranet
Accelerators TCP3d and VCP2 (C6655/57 Only)

Wiki Notes Related to the KeyStone Device Architecture

• MemoryProtectionOnKeystoneDevices
• Software Transactional Memory

Wiki Articles Related to the KeyStone Device Architecture

• Adding An STM Node to CCSv5 Target Configuration
• Adding an ETB Node to the CCSv5 Target Configuration
• BIOS MCSDK 2.0 Getting Started Guide
• BIOS MCSDK 2.0 User Guide
• Bios MCSDK 2.0 API Documentation Locations
• Bios MCSDK 2.0.2 IBL Update
• C6000 Linux Support
• Connecting To An LCEVM with CCS
• Keystone Architecture Advanced Debug Capabilities
• Keystone/Trainings
• MCSDK HUA Demonstration Guide
• MCSDK Image Processing Demonstration Guide
• Multicore Navigator for Dummies
• Multicore System Analyzer
• Software libraries
• TMDSEVM6657L EVM Hardware Setup
• TMDXEVM6618LXE EVM Hardware Setup
• TMDXEVM6670L EVM Hardware Setup
• TMDXEVM6678L EVM Hardware Setup
• Visualizing Common Platform Tracer Data On The Keystone Architecture

White Papers

• How to edit FPGA registers on the EVMs
• Using Trace for Power Profiling
• Great article on setting up interrupts on Keystone devices, and GEL file for interrupt configuration debug
• MatLab Mexing example

Keystone EVM Info

• EVM Support website
• Documentation and scripts for setting up N.A.T. MCH SRIO-Gen2 switch to work with TI's C66x EVMs
• Files for enabling EMAC0 on EVM's AMC connector
• C6678EVM ECN and Enhancements (See Known Issues list)
• EVM Hyperlink connector and SATA-III cable reference: Molex Connector PN 76867-0011, Cable PN 1110670200
• Email Support for EVM HW questions
• MSP430 MMC Code for low-cost EVMs - UPDATED to support NAT, Advantech, and Vadatech MCH cards
• CCSv5.0.x Free CCS licenses for C66x EVMs [Activation Instruction - Step 2]
• CCSv5.1/5.2 Free CCS licenses for C66x EVMs [Activation Instruction - Step 2]
• Updating EMUpacks for CCS
• Updating Keystone EMUpacks for CCS
• XDS560v2 Emulator connection failures and exiting Emulator Safe Mode - usage note
• Steps Needed to use XDS200 Emulator - erase ccs_base\common\targetdb\connections\XDS2XXUSB_Connection.xml and update EMUpack through CCS to 5.0.825.0 or later
• CCS -clean option for clearing cache and recognizing newly installed devices from EMUpacks

Keystone ROM Boot Examples and Reference code

• C6670 PG 1.0 Boot ROM Source Code
• C6678 PG 1.0 Boot ROM Source Code

Debug

• C6678 Debug Gel Script
• C6670 Debug Gel Script
• Keystone SRIO Debug Gel Script
• Keystone Architecture Advanced Debug Capabilities
• CToolsLib
• C6678 Interrupt debug gel

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