Keystone Device Architecture

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Keystone Multicore DSPs
peripherals set #1 peripherals set #2 accelerator set #1 accelerator set #2
1 TMS320C66x DSP TMS320C6654 TMS320C6655 TMS320C6671
2 TMS320C66x DSP TMS320C6657 TMS320C6672
4 TMS320C66x DSP TMS320C6670 TMS320C6674
8 TMS320C66x DSP TMS320C6678


C6670 - Communication Optimized C6671, C6672, C6674, C6678 - General Purpose
TMS320C6670
{{{block_diagram_caption
Useful Links for the C6670:
Product Folder
Training
E2E Forum
TMS320C6678
{{{block_diagram_caption
Useful Links for the C6678:
Product Folder
Training
E2E Forum
  • Next Generation C66x CorePac
    • 4 C66x Cores @ 1.0 GHz - 1.2 GHz
  • Next Generation C66x CorePac
    • 1 to 8 C66x Cores @ 1.0 GHz - 1.25 GHz; for C6672: 1 - 1.5 GHz
    • Available Options: 1, 2, 4 and 8 Core Devices
  • Memory Architecture
    • 1 MB Local L2 per core; total: 4 MB
    • 2 MB Multicore Shared Memory
  • Memory Architecture
    • 512 kB Local L2 per core; total: 512 kB, 1 MB, 2 MB, 4 MB
    • 4 MB Multicore Shared Memory
  • Peripherals & Switch Fabric
    • DDR3 64 bit
    • RapidIO, PCIe, UART, SPI
    • OBSAI/CPRI
    • SGMII with Packet & Security Accelerators
    • HyperLink, TeraNet
  • Peripherals & Switch Fabric
    • DDR3 64 bit, EMIF16
    • RapidIO, PCIe, UART, SPI
    • TSIP
    • SGMII with Packet & Security Accelerator
    • HyperLink, TeraNet
  • Accelerators
    • FFTc, VCP2, TCP3e, TCP3d
  • Accelerators
    • <see SGMII>
C6654 C6655, C6657
TMS320C6654
{{{block_diagram_caption
Useful Links for the C6654:
Product Folder
Training
E2E Forum
TMS320C665x
{{{block_diagram_caption
Useful Links for the C665x:
Product Folder
Training
E2E Forum
  • Next Generation C66x CorePac
    • 1 C66x Core @ 850MHz
  • Next Generation C66x CorePac
    • 1 or 2 C66x Cores @ 1 - 1.25 GHz
  • Memory Architecture
    • 1 MB Local L2
  • Memory Architecture
    • 1 MB Local L2 per core; total: 1 MB, 2 MB
    • 1 MB Multicore Shared Memory
  • Peripherals & Switch Fabric
    • SGMII, PCIe, McBSP, UART, SPI, I2C, UPP, 32 bit DDR3, EMIF15
    • Teranet
  • Peripherals & Switch Fabric
    • SGMII, PCIe, McBSP, UART, SPI, I2C, UPP, 32 bit DDR3, EMIF15
    • Teranet
    • RapidIO and Hyperlink
  • Accelerators
    • <none>
  • Accelerators
    • TCP3d and VCP2




Wiki Notes Related to the KeyStone Device Architecture

Wiki Articles Related to the KeyStone Device Architecture

White Papers

Keystone EVM Info

Keystone ROM Boot Examples and Reference code

Debug

E2e.jpg
  • For technical support on MultiCore devices, please post your questions in the C6000 MultiCore Forum
  • For questions related to the BIOS MultiCore SDK (MCSDK), please use the BIOS Forum

Please post only comments related to the article Keystone Device Architecture here.

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