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Multicore Software Development Kit

Image Processing Demonstration

User's Guide

Last updated: 4/12/2012

Overview

The Image Processing Demonstration illustrates the integration of key components in the Multicore Software Development Kit (MCSDK) on Texas Instruments (TI) multicore DSPs and System-on-Chips. The purpose of the demonstration is to provide a multicore software development framework on an evaluation module (EVM).

This document covers various aspects of the demonstration application, including a discussion on the requirements, software design, instructions to build and run the application, and troubleshooting steps. Currently, only SYS/BIOS is supported as the embedded OS.

This application shows implementation of an image processing system using a simple multicore framework. This application will run TI image processing kernels (a.k.a, imagelib) on multiple cores to do image processing (eg: edge detection, etc) on an input image.

Note: The current implementation of this demonstration is not optimized. It should be viewed as the initial implementation of the BIOS MCSDK software eco-system for creating an image processing functionality. Further analysis and optimization of the demonstration are under progress.

Note: There are two versions of the demo provided in the release. The IPC based version runs on multiple cores and shows explicit IPC programming framework. The other one is a serial version of the demo, which runs on the simulator. Unless explicitly specified, the IPC based version is assumed in this document.

Requirements

The following materials are required to run this demonstration:

• TMS320C6x low cost EVMs [Check Image Processing release notes for supported platforms]
• Power cable
• Ethernet cable
• Windows PC with CCSv5

Software Design

The following block diagram shows the framework used to implement the image processing application:

The following diagram shows the software pipeline for this application: .

More about processing algorithms

The application will use imagelib APIs for its core image processing needs.

Following steps are performed for edge detection

• Split input image into multiple overlapping slices
• If it is a RGB image, separate out the Luma component (Y) for processing (See YCbCr for further details)
  

• Run Sobel operator (IMG_sobel_3x3_8) to get the gradient image of each slices

• Run the thresholding operation ( IMG_thr_le2min_8) on the slices to get the edges

• Combine the slices to get the final output

Framework for multicore

The currant framework for multicore will be IPC Message Queue based framework. Following are the overall steps (the master and threads will be run on 1 or more cores)

• The master thread will preprocess the input image (described in User interface section) to make a gray scale or luma image

• The master thread signal each slave thread to start processing and wait for processing complete signal from all slave threads

• The slave threads run edge detection function (described above) to generate output edge image of the slice

• Then the slave threads signal master thread indicating the processing completed

• Once master thread receives completion signal from all threads it proceeds with further user interface processing (described in User interface section)

Profiling of the algorithm

• The profiling information live processing time will be presented at the end of the processing cycle

• Core image processing algorithms is instrumented using UIA for analysis and visualization using MCSA (Multicore System Analyzer)

User interface

The user input image will be BMP image. The image will be transferred to external memory using NDK (http). Following are the stapes describing application user interface and their interaction

• At the time of bootup the board will bring configure IP stack with static/dynamic IP address and start a HTTP server

• The board will print the IP address in CCS console

• The user will use the IP address to open the index/input page (see link Sample Input Page)

• The application will support BMP image format

• The master thread will extract the RGB values from BMP image
  

• Then the master thread will initiate the image processing (as discussed above) and wait for its completion

• Once the processing completes, it will create output BMP image

• The master thread will put input/output images in the output page (see link Sample Output Page)

Run Instructions

The pre-compiled libraries are provided as a part of MCSDK release.

Please follow the procedures below to load images using CCS and run the demo.

Please refer the hardware setup guide for further the setup details.

• Connect the board to a Ethernet hub or PC using Ethernet cable.
• The demo runs in Static IP mode if User Switch 1 (SW9, position 2) is OFF else if it is ON then it runs in DHCP mode. See the Hardware Setup section for the location of User Switch 1.  
• If it is configured in static IP mode, the board will come up with IP address 192.168.2.100, GW IP address 192.168.2.101 and subnet mask 255.255.254.0
• If it is configures in DHCP mode, it would send out DHCP request to get the IP address from a DHCP server in the network.
• There are two images to be loaded to master (core 0) and other cores. The core 0 to be loaded with <MCSDK INSTALL DIR>\demos\image_processing\ipc\evmc66##l\master\Debug\image_processing_evmc66##l_master.out image and other cores (referred as slave cores) to be loaded with <MCSDK INSTALL DIR>\demos\image_processing\ipc\evmc66##l\slave\Debug\image_processing_evmc66##l_slave.out image.
• Connect the debugger and power on the board.
• In CCS window, launch the target configuration file for the board.
• It should open debug perspective and open debug window with all the cores.
• Connect to all the cores and load image_processing_evmc66##l_master.out to core 0 and image_processing_evmc66##l_slave.out to all other cores.
• Run all the cores, in the CIO console window, the board should print IP address information (for eg: Network Added: If-1:192.168.2.100)
• Open a web browser in the PC connected to the HUB or the board.
• Enter the IP address of the board, it should open up the image processing demo web page.
• Please follow the instructions in the web page to run the demo.
• Note that, sample BMP images are provided in <MCSDK INSTALL DIR>\demos\image_processing\images
  

Note: If you want to run the demo in static IP address mode, make sure the host PC is in same subnet or can reach the gateway. A sample setup configuration is shown below.

In Windows environment

Set up TCP/IP configuration of ‘Wired Network Connection’ as shown in Wired Network Connection in Windows.

In Linux environment

Run following command to set the static IP address for the current login session on a typical Linux setup.

sudo ifconfig eth0 192.168.2.101 netmask 255.255.254.0

Build Instructions

Please follow the steps below to re-compile the IPC based demo image (These steps assume you have installed the MCSDK and all the dependent packages).

• Open CCS->Import Existing... tab and import project from <MCSDK INSTALL DIR>\demos\image_processing\ipc.
• It should import two projects image_processing_evmc66##l_master and image_processing_evmc66##l_slave.
• Right click on each project->Properties to open up the properties window.
• Goto CCS Build->RTSC and check if in other repository have link to <MCSDK INSTALL DIR> (the actual directory).
• If IMGLIB C66x is unchecked, please select 3.0.1.0 to check it.
• The RTSC platform should have demos.image_processing.evmc66##l.platform.
• The project should build fine.

Software Directory Structure Overview

The IPC based Image Processing Demonstration is present at <MCSDK INSTALL DIR>\demos\image_processing\ipc

• <MCSDK INSTALL DIR>\demos\image_processing\ipc\common directory has common slave thread functions which runs on all cores; The image processing function runs in this slave thread context
• <MCSDK INSTALL DIR>\demos\image_processing\ipc\master directory has main thread, which uses NDK to transfer images and IPC to communicate to other cores to process image
• <MCSDK INSTALL DIR>\demos\image_processing\ipc\slave directory has the initialization function for all slave cores
• <MCSDK INSTALL DIR>\demos\image_processing\ipc\evmc66##l\[master|slave] directory have the master and slave CCS project files
• <MCSDK INSTALL DIR>\demos\image_processing\ipc\evmc66##l\platform directory have the target configuration for the project
• <MCSDK INSTALL DIR>\demos\image_processing\serial directory have the serial version of the implementation
• <MCSDK INSTALL DIR>\demos\image_processing\utils directory have utilities used on the demo, like MAD config files
• <MCSDK INSTALL DIR>\demos\image_processing\images directory have sample BMP images

Image Processing Demo Serial Code Overview

The serial (single core) version of the image processing demo is provided in the package. Please do the following to import and run the project on the CCS simulator

• Import the project image_processing_serial_simc6678 from <MCSDK INSTALL DIR>\demos\image_processing\serial directory
• Assuming the <MCSDK INSTALL DIR> is installed in default directory, the project should build as it is
• The output can be load to a single core in the simulator and should run fine
• The image takes evmc6678l_689x306_618KB.bmp from <MCSDK INSTALL DIR>\demos\image_processing\serial\images directory as input image and outputs evmc6678l_689x306_618KB_edge.bmp in same directory
• Other images can be processed by the program, to enable the feature, open the file mcip_master_main.c from <MCSDK INSTALL DIR>\demos\image_processing\serial\src directory. Un-comment line with /*#define USER_INPUT_FILE*/, re-compile, load and run the project. It should ask for the input and output image file name

Multicore System Analyzer integration and usage

The System Analyzer provides correlated realtime analysis and visiblity into application running on single or multicore. Analysis and visibility includes Execution Graph, Duration Analysis, Context Aware Profile, Load Analysis and Statistics Analysis. Basic instrumentation using Unified Instrumentation Architecture (UIA) collects data in realtime and transport via Ethernet or JTAG to host where it it decoded, correlated, analyzed and visualized.

System Analyzer is automatically added to CCS5.0 by the MCSDK istaller. CCS5.1 is shipped with the System Analyzer included.

The Image Processing Demo has been instrumented for duration/benchmark and CPU load analysis. Detailed information on running the demo with System Analyzer is provided in System Analyzer and the MCSDK Demo page.

Image Processing Demo Analysis with Prism

This section we will use Prism software to analyze the serial version of image processing demo. The steps below would assume Prism with C66x support is installed in the system and user completed the Prism Getting Started - Tutorials provided in the help menu.

Bring up the demo with Prism software

• Bring up the CCS as specified in the Prism documentation
• Edit macros.ini file from <MCSDK INSTALL DIR>\demos\image_processing\serial directory and change ../../../../imglib_c66x_#_#_#_# to static path to IMGLIB package
• Open Import Existing CCS Eclipse Project and select search directory <MCSDK INSTALL DIR>\demos\image_processing\serial
• Check Copy projects into workspace and click Finish. This will copy the project to the workspace for Prism.
• Clean and re-compile the project
• Open the C6678 simulator, load the image to core0
• Open Tools->GEL files, select Load GEL and load/open tisim_traces.gel from <CCSv5 INSTALL DIR>\ccs_base_####\simulation_csp_ny\env\ccs\import directory
• Then select CPU Register Trace->StartRegTrace to start the trace, then run the program, wait till it finishes, then select CPU Register Trace->StopRegTrace to stop the trace
• Open Prism->Show Prism Perspective. It will start Prism Perspective
• Right click on the project and select Create New PAD File, it would open the New Prism Analysis Definition window, hit next
• It will open Architecture Selection window, select C6671 (single core) template. Then select Finish to open PAD file
• Select Run->Debug Configurations->prismtrace, this will convert the simulator generated traces to the traces required by Prism
• The PAD window should have filled in with default trace (PGSI, PGT) file names generated in above step
• Select Read Trace to read the trace
• After it read the trace, then select the complete trace from overview window and hit Load Slice
• The Functions tab will show the functions and their cycle information during the execution
• Observe the Core 0 scheduling in the schedule window, you can place a marker for this run

What If analysis

The Prism tool allows user to analyze What If scenarios for the code

• What If the code is run on multiple cores
  • In the function window, right click on process_rgb function, select Force Task and hit Apply. This would make process_rgb function simulated as a separate task
  • In the Architecture tab, select C6678 (8 Core) template, hit Apply
  • Observe in Schedule tab, the change in execution when selected the process_rgb is simulated to run on 8 cores
  • A marker can be placed to compare the improvement
• What If the dependencies are removed
  • The Dependencies window helps to see and analyze the dependencies (which are preventing the task to be executed in multiple cores simultaneously)
  • Un-check Serialized check-boxes against dependency rows and hit Apply
  • Add the comparison marker in the Schedule tab and check the improvement

The Prism supports more functionality then described in this section. Please see Prism documentation for more information.

Multicore booting using MAD utilities

The detailed information on the Multicore Application Deployment a.k.a MAD utility is provided in MAD user guide page.

This section will provide you the detail instructions on how the tool and boot the demo from flash/ethernet.

Linking and creating bootable application image using MAD utilities

The BIOS MCSDK installation provides MAD tool in <MCSDK INSTALL DIR>\tools\boot_loader\mad-utils. This package contains necessary tools to link the application to a single bootable image.

The image processing demo has following updates to create MAD image:

• The master and slave images are linked with --dynamic and --relocatable options.
• The MAD config files used to link the master and slave programs are provided in <MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\config-files. Following are few items to note on the config file.
  • maptoolCfg_evmc#####.json has the directory and file name information for the tools
  • deployment_template_evmc#####.json has the deployment configuration (it has device name, partition and application information). Following are some more notes on the configuration file.
    • For C66x devices, the physical address is 36 bits and virtual address is 32 bits for external devices, this includes MSMC SRAM and DDR3 memory subsystem.
    • The secNamePat element string is a regular expression string.
    • The sections bss, neardata, rodata must be placed in one partition and in the order it is shown here
• The build script <MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\build_mad_image.bat can be used to re-create the image

Note: The compilation will split out lots of warning like Incompatible permissions for partition ..., it can be ignored for now. This is due to mis-match in partition permissions wrt. the sections placed in the partition

• The bootable image is placed in <MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\images

Pre-link bypass MAD image

Please see MAD user guide for more information on pre-link bypassed MAD image. The build script build_mad_image_prelink_bypass.bat can be used to build images with this mode.

Booting the application image using IBL

This image can be booted using IBL bootloader.

Following things to be noted on booting the image

• The image type/format is ibl_BOOT_FORMAT_BBLOB, so the IBL needs to be configured to boot this format
• The branch address (Branch address after loading) of the image [it is set to 0x9e001040 (or 0x80001040 if you are using BIOS MCSDK v 2.0.4 or prior) in MAL application], is different from default IBL boot address, so the IBL configuration needs to be updated to jump to this address

The following sections will outline the steps to boot the image from Ethernet and NOR using IBL. Please see IBL documentation on the detail information on booting.

Booting from Ethernet (TFTP boot)

• Change IBL configuration: The IBL configuration parameters are provided in a GEL file <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cConfig.gel. All the changes needs to be done in the function setConfig_c66##_main() of the gel file.
  • The IBL configuration file sets PC IP address 192.168.2.101, mask 255.255.255.0 and board IP address as 192.168.2.100 by default. If these address needs to be changed, open the GEL file, change ethBoot.ethInfo parameters in function setConfig_c66##_main()
  • Make sure the ethBoot.bootFormat is set to ibl_BOOT_FORMAT_BBLOB
  • Set the ethBoot.blob.branchAddress to 0x9e001040 (or 0x80001040 if you are using BIOS MCSDK v 2.0.4 or prior).
  • Note that the application name defaults to app.out

menuitem "EVM c66## IBL";
 
hotmenu setConfig_c66##_main()
{
 ibl.iblMagic = ibl_MAGIC_VALUE;
 ibl.iblEvmType = ibl_EVM_C66##L;
 
 ...
 
 ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
 ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
 ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
 ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
 
 
 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
 
 ...
 
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
 
 ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x9e000000 /*0x80000000 for BIOS MCSDK v2.0.4 or prior*/; /* Load start address */
 ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
 ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x9e001040 /*0x80001040 for BIOS MCSDK v2.0.4 or prior*/; /* Branch address after loading */
 
 ibl.chkSum = 0;
}

• Write IBL configuration:
  • Connect the board using JTAG, power on the board, open CCS, load the target and connect to core 0. Select Tools->GEL Files and in the GEL Files window right click and load GEL. Then select and load <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cConfig.gel.
  • Load I2C writer <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cparam_0x51_c66##_le_0x500.out to Core 0 and run. It will ask to run the GEL in console window. Run the GEL script from Scripts->EVM c66##->setConfig_c66##_main.
  • Open the CCS console window and hit enter to complete the I2C write.

• Booting the image:
  • Disconnect the CCS from board, power off the board.
  • Connect ethernet from board to switch/hub/PC and UART cables from board to PC.
  • Make sure your PC have the IP address specified above.
  • Set the board dip switches to boot from ethernet (TFTP boot) as specified in the hardware setup table (TMDXEVM6678L TMDXEVM6670L)
  • Copy the demo image <MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\images\mcip-c66##-le.bin to tftp directory and change its name to app.out
  • Start a tftp server and point it to the tftp directory
  • Power on the board. The image will be downloaded using TFTP to the board and the serial port console should print messages from the demo. This will also print the configured IP address of the board
  • Use the IP address to open the demo page in a browser and run the demo

Booting from NOR

• Change IBL configuration: The IBL configuration parameters are provided in a GEL file <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cConfig.gel. All the changes needs to be done in the function setConfig_c66##_main() of the gel file.
  • Make sure the norBoot.bootFormat is set to ibl_BOOT_FORMAT_BBLOB
  • Set the norBoot.blob[0][0].branchAddress to 0x9e001040 (or 0x80001040 if you are using BIOS MCSDK v 2.0.4 or prior)

menuitem "EVM c66## IBL";
 
hotmenu setConfig_c66##_main()
{
 ibl.iblMagic = ibl_MAGIC_VALUE;
 ibl.iblEvmType = ibl_EVM_C66##L;
 
 ...
 
 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
 ibl.bootModes[0].port = 0;
 
 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
 ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */ 
 ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
 ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */ 
 ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
 ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x9e000000 /*0x80000000 for BIOS MCSDK v2.0.4 or prior*/; /* Image 0 load start address in LE mode */
 ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
 ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x9e001040 /*0x80001040 for BIOS MCSDK v2.0.4 or prior*/; /* Image 0 branch address after loading in LE mode */
 
 ...
 
 ibl.chkSum = 0;
}

• Write IBL configuration:
  • Connect the board using JTAG, power on the board, open CCS, load the target and connect to core 0. Select Tools->GEL Files and in the GEL Files window right click and load GEL. Then select and load <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cConfig.gel.
  • Load I2C writer <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cparam_0x51_c66##_le_0x500.out to Core 0 and run. It will ask to run the GEL in console window. Run the GEL script from Scripts->EVM c66##->setConfig_c66##_main
  • Open the CCS console window and hit enter to complete the I2C write

• Write NOR image:
  • Copy application image (<MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\images\mcip-c66##-le.bin) to <MCSDK INSTALL DIR>\tools\writer\nor\evmc66##l\bin\app.bin
  • Connect the board using JTAG, power on the board, open CCS, load the target and connect to core 0. Make sure the PLL and DDR registers are initialized from the platform GEL (if it is not done automatically, run Global_Default_Setup function from the GEL file). Load image <MCSDK INSTALL DIR>\tools\writer\nor\evmc66##l\bin\norwriter_evm66##l.out
  • Open memory window and load the application image (<MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc66##l\images\mcip-c66##-le.bin) to address 0x80000000
  • Be sure of your Type-size choice 32 bits
  • Hit run for NOR writer to write the image
  • The CCS console will show the write complete message

• Boot from NOR:
  • Disconnect CCS and power off the board
  • Set the board dip switchs to boot from NOR (NOR boot on image 0) as specified in the hardware setup table (TMDXEVM6678L TMDXEVM6670L)
  • Connect ethernet cable from board to switch/hub
  • Connect serial cable from board to PC and open a serial port console to view the output
  • Power on the board and the image should be booted from NOR and the console should show bootup messages
  • The demo application will print the IP address in the console
  • Use the IP address to open the demo page in a browser and run the demo

For technical support on MultiCore devices, please post your questions in the C6000 MultiCore Forum For questions related to the BIOS MultiCore SDK (MCSDK), please use the BIOS Forum Please post only comments related to the article MCSDK Image Processing Demonstration Guide here.

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