MSP430 BOR Considerations

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The below are recommendations on how to avoid experiencing issues related to brown-out with the MSP430(For devices with NO BOR protection circuit: MSP430F10x1, MSP430F11x1, MSP430F12x, MSP430F13x, MSP430F13x1, MSP430F14x, MSP430F14x1):

1. The CPU begins code execution after the reset is released. However, VCC may not have ramped to VCC(min) at that time. The user must ensure the default DCO settings are not changed until VCC reaches VCC(min). An external voltage supervisor circuit can be used to determine when VCC reaches VCC(min). Alternatively a software delay can be used after power up before CPU clock is altered.

If this is not followed, the CPU may jump to an unspecified location in memory and execute unwanted instructions. The only way to recover the device in this scenario is with a power-cycle. Please see MSP430x1xx Users Guide Note (pg 20).

2-These devices must follow the dV/dT rise & fall time of Vcc requirement as described in the device datasheet to meet POR requirements. For example, the MSP430F169 datasheet gives this information on pages 32 and 33.

3-If it is required to perform any "In-system Flash programming," ensure that the minimum Vcc required for writing to Flash and the required frequency of flash timing generator are met. For example the variable F(ftg) on page 39 of the F149 device datasheet gives relevant data.

4. It is important to follow the Vcc (vs) Freq chart listed in the datasheet (example F149 d/s see pg 24) at all times to be within specification.

5. Please test your setup using a pin-compatible BOR device. This is important because it does not involve any hardware or software changes unless you want to configure the on-chip SVS.

6. Please also follow the min requirement for pull-up resistor and capacitor to GND on Reset pin per Family User’s Guide and FET User’s Guide.

7. "On devices with no brownout-reset circuit, If power to the MSP430 is cycled, the supply voltage VCC must fall below Vmin to ensure that a POR signal occurs when VCC is powered up again. If VCC does not fall below Vmin during a cycle or a glitch, a POR may not be generated and power-up conditions may not be set correctly. In this case, a low level on RST/NMI may not cause a POR and a full power-cycle will be required. See device-specific datasheet for parameters." –from 1xx User’s Guide, page 2-3

8. To debug such issues, it may be best to probe the Vcc, Reset and MCLK lines to see any unusual changes on these.

For technical support please post your questions at http://e2e.ti.com. Please post only comments about the article MSP430 BOR Considerations here.