From Texas Instruments Embedded Processors Wiki

C6670 - Communication Optimized	C6678 - General Purpose
TMS320C6670 Useful Links for the C6670: Product Folder Training E2E Forum	TMS320C6678 Useful Links for the C6678: Product Folder Training E2E Forum
Next Generation C66x CorePac 4 C66x Cores @ 1.0 GHz - 1.2 GHz	Next Generation C66x CorePac Upto 8 C66x Cores @ 1.0 GHz - 1.5 GHz (1.5 GHz for two devices only) Available Options: 1, 2, 4 and 8 Core Devices
Memory Architecture 4 MB Local L2/Core (1 MB per core) 2 MB Multicore Shared Memory	Memory Architecture 4 MB Local L2/Core (512 KB per core) 4 MB Multicore Shared Memory
Peripherals & Switch Fabric RapidIO, OBSAI/CPRI, SGMII, PCIe, UART, SPI, DDR3 FFTc, VCP2, TCP3e, TCP3d, Packet & Security Accelerators HyperLink, TeraNet	Peripherals & Switch Fabric RapidIO, TSIP, SGMII, PCIe, UART, SPI, DDR3, EMIF16 Packet & Security Accelerator HyperLink, TeraNet
Accelerators FFTc, VCP2, TCP3e, TCP3d, Packet & Security Accelerators	Accelerators Packet & Security Accelerator

Technical Specifications

Technical specifications can change between devices, peripherals types, coprocessors and device families. Always refer to the data manual and errata for a particular device for Technical Specifications.

Getting Started

TI's KeyStone multicore architecture implemented in C66x generation of DSPs offer the industry's first 10-GHz DSP with unsurpassed performance and a variety of on-chip resources that can be rapidly and effectively deployed to meet the most demanding requirements. The KeyStone devices come in one, two, four or eight cores with each high-speed core (1.5 GHz, 1.25 GHz or 1 GHz) allowing up to 320 GMACs/160 GFLOPs for 1.25 GHz and 256 GMACs/128 GFLOPs for 1 GHz.

The C66x devices are designed to be backwards code compatible with TI's previous generation of C6000 fixed and floating-point DSP cores ensuring software portability.

If you are new to KeyStone devices, please check the following links to get yourself familiar.

KeyStone Device Family

The following links provide easy access to more advanced technical information regarding KeyStone devices. Each link provides access to specific device category on that particular topic

General Purpose Multicore Devices

• TMS320C6671
• TMS320C6672
• TMS320C6674
• TMS320C6678

Wireless Communication Optimized Multicore Device

• TMS320C6670

KeyStone Architecture Overview

• Provides a high performance structure for integrating RISC and DSP core for application specific coprocessor and I/Os
• Provides the flexibility to
  • Include fixed and floating-point computations in the same processing core
  • Targeted co-processing and hardware acceleration
  • Optimized inter-core/inter-element communication
  • Comprehensive connectivity planes: TeraNet2
• Multicore Shared Memory Controller to enable direct access to on-chip shared memory and external double-data-rate three (DDR3) memory
• Multicore Navigator to facilitate and manage communications across the SoC architecture
• HyperLink 50 to interconnect companion devices such as additional coprocessors or other TI SoCs

KeyStone Architecture elements and features

The following table highlights the key elements of KeyStone Architecture devices and the respective features.

KeyStone Device Elements	Features
New C66x CorePac	Next Generation Fixed and Floating-Point DSP Core Clock speeds ranging from 850MHz - 1.5 GHz 1, 2, 4, 8 Core options Enhanced instruction set with backward code compatibility
Memory Architecture	Multicore Shared Memory (MSM) Upto 8 MB of combined memory with fast on and off chip memory access Shared internal memory avoids duplication of critical common code Allows soft partitioning of internal memory between cores. Dynamically shared among all cores Error detection and correction features Memory protection is extended to shared (internal/external) memories. Multicore shared memory controller (MSMC) Enables faster and increased throughput to local and shared internal / external memories Support for pre-fetching reducing the latency gap between local memory and shared internal/external memories. Improved write merging and optimized burst sizes reduce the stalls from/to external memory. External Memory Interface Provides a common managed path to shared external memory (DDR3) for multicore access DDR3 support. 1x16/32/64 data pins upto 1.6 Gbps per data pin DDR3 EMIF supports Error detection and correction Address extension Provides a virtual address space for each core Extends the physical address space beyond 4 Gbytes using 36-bit addressing.
Multicore Navigator	Primary data movement engine in KeyStone Architecture Enables data movement between various system elements without using CPU overhead
Network Co-Processor and Accelerators	Cost effective implementation to off-load wireless and secure networking functions from DSP
TeraNet	Provides the capability to expand the C66x to include hardware acceleration or other auxiliary processors Very low latency and protocol light connectivity to other Hyperlink devices including FPGAs
Peripherals and I/O Interfaces	High bandwidth peripherals that operate allowing simultaneous data transfer to prevent bottle necks RapidIO v2.1 - 4lanes @ 5Gbps with 1x and 4x support PCIe x 2 - 2lanes, running independent of RapidIO

External Interfaces

The following are KeyStone devices external interfaces Wiki categories. Also refer to your device specifications for interface details specific to your device.

• PCI Express (PCIe) Gen II Port
• Universal Asynchronous Receiver / Transmitter (UART)
• Serial Port Interface (SPI)
• Inter IC Control Module (I2C)
• General Purpose IO (GPIO) Module
• Serial Rapid IO (SRIO)
• SGMII ports with embedded switch
• EMIF-16

Application Specific Interfaces

For Wireless Applications

• Antenna Interface 2 (AIF2)

For Media Gateway Applications

• Telecommunication Serial Port (TSIP)

Debug / Trace - Diagnostic Enhancements

Debug Overview

For Multicore devices it is vital to have enough visibility to faciliate debug at the system level. KeyStone devices provide sufficient hooks to faciliate the visibility as well as monitor large data move through the chip to understand available bandwidth and latency from a system context.

Refer to the C66x debug features including triggers, statistics, and traces for more details.

The following Diagnostic enhancements are available in KeyStone devices.

• Advanced Event Triggering (AET)
• AETLib
• Embedded Trace Buffer (ETB)
• Trace
• Debugging with Trace

KeyStone Trace Capabilities

Leveraging trace technology capabilities, the KeyStone device family supports both Core Trace and System Trace.

Core Trace is a debug and profiling technology that provides a detailed historical record of application code execution, timing, data access and events. Core Trace works in real-time and does not impact the execution of the system.

System Trace (STM) provides formatting and transport for instrumentation messages that can be integrated into your application and for system modules that provide debug and profile monitoring services, such as the Common Platform Tracer (CPT).

Common Platform Tracer (CPT) modules facilitate real time data collection from critical slave buses across the system providing real-time performance / throughput visibility within the SoC. CPT modules format and export both profile data and slave bus events after applying various filters. CPT modules operate with no impact to the execution of the system.

The data collected from System Trace instrumentation and from CPT modules in turn can be used in data analysis tools to infer and tune software applications to gain maximum efficiency.

Each CorePac module has a dedicated Embedded Trace Buffer for Core Trace and there is a chip level Embedded Trace Buffer to capture System Trace. Both Core Trace and System Trace can also be exported over the EMU pins for remote collection by a trace enabled XDS.

For more details refer to Common Platform Tracer details and Common Platform Tracer Examples.

Applications

Application Segments for KeyStone Devices

KeyStone Devices offer

Mission Critical Military Avionics Public Safety Medical Imaging Ultrasound Endoscopy MRI / CT Scan Emerging modalities Test & Automation Wafer / LCD Inspection Niche printing / scanning Emerging Video Media & Networking Applications Video Infrastructure Mobile Video Transcode / Distribution IMS Voice / Video Services 2G / 3G Transcoding & Wireless MGW Session Border Control, Border Gateways Class 4/5 Switch Replacement

Support for both fixed and floating point processing Enhanced memory architecture with large on chip memmory Faster on chip data transfers with new multicore Navigator TeraNet switch fabric with 2 TB of bandwidth Low power, Extended temperature range 1, 2, 4, 8 Core options Multiple high speed peripherals Focused security & network coprocessors Enhanced instruction set with backward code compatibility Memory ECC (Error Correction Code) Supported by world class, robust Tools & CCS IDE

End Equipment Solutions

Refer to the following end-equipment solutions using multi-core devices.

• ATCA Solutions
• CT Scanner
• Cable Modem Termination System
• Digital Signage
• MRI: Magnetic Resonance Imaging
• Machine Vision: Camera
• Machine Vision: Frame Grabber
• Military and Avionics Imaging
• Military: Munitions and Targeting
• Military: Radar/Sonar
• Point-to-Point Microwave Backhaul
• Power Line Communication Modem
• Signal/Waveform Generator
• Ultrasound System
• Ultrasound System: Portable
• Vector Signal Analyzer
• Vector Signal Generator
• Video Analytics Server
• Video Broadcasting & Infrastructure: Scalable Platform
• Video Broadcasting: IP-Based Multi-Format Transcoder
• Wireless Communications Tester
• Wireless Repeater
• X-ray: Baggage Scanner

Training and Workshops

Visit the KeyStone Training & Events to access archived workshop material and on-line courses.

Also, be sure to check out the Introduction to the Multicore Software Development Kit (MCSDK) Training.

Development Tools

The Development Tools for KeyStone devices category includes information on:

• TMDXEVM6678 Evaluation Module
• TMDXEVM6670 Evaluation Module

They provide options for evaluating new C66x high-performance multicore DSPs.

Software tools:

• Code Composer Studio
• SYS/BIOS and Linux Multicore Software Development Kits

Other Resources / White Papers:

To discuss technical questions, the E2E Community is a great resource. Visit e2e.ti.com. Also refer to technical documents, User guides, White Papers through the device specific web links.

• C6672/74/78 Technical Documentation
• Multicore Programming

Forums on the E2E site include:

• C66x Multicore DSP Forums
• Development Tools (CCS, Compiler, DSP/BIOS) Forums

Wiki Notes Related to the KeyStone Device Architecture

• MemoryProtectionOnKeystoneDevices
• Software Transactional Memory

Wiki Articles Related to the KeyStone Device Architecture

• Adding An STM Node to CCSv5 Target Configuration
• Adding an ETB Node to the CCSv5 Target Configuration
• BIOS MCSDK 2.0 Getting Started Guide
• BIOS MCSDK 2.0 User Guide
• Bios MCSDK 2.0 API Documentation Locations
• Bios MCSDK 2.0.2 IBL Update
• C6000 Linux Support
• Connecting To An LCEVM with CCS
• Keystone Architecture Advanced Debug Capabilities
• Keystone/Trainings
• MCSDK HUA Demonstration Guide
• MCSDK Image Processing Demonstration Guide
• Multicore System Analyzer
• Software libraries
• TMDXEVM6618LXE EVM Hardware Setup
• TMDXEVM6670L EVM Hardware Setup
• TMDXEVM6678L EVM Hardware Setup

Keystone EVM Info

• EVM Support website
• Files for enabling EMAC0 on EVM's AMC connector
• C6678EVM ECN and Enhancements (See Known Issues list)
• EVM Hyperlink connector and SATA-III cable reference: Molex Connector PN 76867-0011, Cable PN 1110670200
• Email Support for EVM HW questions
• MSP430 MMC Code for low-cost EVMs - UPDATED to support NAT, Advantech, and Vadatech MCH cards
• CCSv5.0.x Free CCS licenses for C66x EVMs [Activation Instruction - Step 2]
• CCSv5.1 Free CCS licenses for C66x EVMs [Activation Instruction - Step 2]

Keystone ROM Boot Examples and Reference code

• C66x Secondary Bootloader for SRIO, EMAC, PCIe with PLL Fix

Leave a Comment