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OMAP-L137 Hardware Design Guide

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Hardware Design Timeline →

Constructing the Block Diagram Selecting the Boot Mode Confirming Pin Multiplexing Compatibility Confirming Electrical and Timing Compatibility Designing the Power Subsystem Designing the Clocking Subsystem Floorplanning the PCB Creating the Schematics Laying out the PCB Testing / Debugging



Welcome to the OMAP-L137/C6747/AM1707 Hardware Design Guide.  The purpose of this guide is to walk hardware designers through the various stages of designing a board around OMAP-L137/C6747/AM1707.  The guide follows the structure shown in the Hardware Design Timeline above.  Each design stage in the Timeline links to a collection of useful documentation, application notes, and design recommendations pertaining to that stage.  Using this Guide, hardware designers can efficiently locate the resources they need at every step in the board design flow.

Constructing the Block Diagram

The first step in designing the hardware platform is to create a detailed block diagram.  The block diagram should contain all major system ICs and illustrate which I/O ports are used for device interconnection.  Below is a collection of resources to aid in the Block Diagram creation process.

Selecting the Boot Mode

The block diagram should also indicate which interface will be used for booting the processor.  Upon coming out of reset, the processor must boot up by loading its application code from external storage. The application code can be loaded from a ROM or can be downloaded from another processor in the system.  The processor contains a primary bootloader burned into its internal ROM which is run by the processor after coming out of reset. This primary bootloader performs some critical initial tasks and then loads application code from the external interface specified by the processor boot configuration pins. See the below information for selecting an implementing the right boot mode for your system.

Confirming Pin Multiplexing Compatibility

The processor uses internal pin multiplexing to allow for maximum functionality in the smallest and lowest cost package.  Due to this pin multiplexing, not all processor interfaces are always available simultaneously.See the Terminal Functions section of the datasheet for complete details on the pin multiplexing.  Also see the below information for tools and tips related to pin multiplexing.

Confirming Electrical and Timing Compatibility

A key step in the hardware design before beginning schematic capture is to confirm both DC and AC electrical compatibility between processor and the other ICs connected to it.  See the below collection of information to aid in confirming the system's electrical compatibility

  • Note: TI provides PCB layout specifications for the following interfaces, eliminating the need to perform electrical analysis:
    • USB

Designing the Power Subsystem

Once the block diagram has been validated for pin multiplexing, electrical, and timing compatibility, the power sub-system can be designed. See the below resources on estimating processor power consumption and designing a matching power subsystem.

  • Key Considerations for designing the Power Subsystem:
    • Make sure to follow the supply sequencing requirements listed in the datasheet
    • Make sure to properly filter the PLL power supply according to the recommendations listed in the datasheet

Designing the Clocking Subsystem

In addition to the power subsystem, the clocking subsystem needs to be designed to provide appropriate clocks to all ICs in the system. These clocks can be created by pairing crystals with internal oscillators within the system ICs, or they can be created by a separate clock generator. See the below information on designing the clocking subsystem for your design.

Download the the new PLL, System and Peripheral Clock Calculation spreadsheet for OMAP-L137, C6747/5/3 and AM17x devices

Floorplanning the PCB

Before beginning schematic capture, it is recommended to floor plan the system PCB to determine the interconnect distances between the various system ICs. See the below information on floor planning your PCB.

  • TBD: Why and How to floor plan your PCB before starting schematic capture

Creating the Schematics

At this point in the design, it is time to start capturing the schematics. See the below collection of information to aid you in creating the schematics for your design.

  • Key Considerations for creating the Schematics:
    • SDRAM (and other) output clocks are internally looped back
    • Don’t forget to install a JTAG connection
    • JTAG: Make sure to use the RTCK pin

Laying out the PCB

After completing schematic capture, see the below information on laying out the PCB for your system:


Once your custom PCB has been produced and assembled, refer to the below information on bringing-up and debugging the system.

  • See the below information on using GEL Files to aid in configuring your design during debug/development
    • OMAP-L137/C6747/AM1707 Debug GEL File: This can be used with CCS to print out useful debug information such as silicon revision, bootloader error messages, current PC and PSC states, and more.
  • Below is a collection of information on using the TI provided Booting Tools for OMAP-L137
    • Serial UART Boot and Flash Loading Utility for OMAP-L137/C6747/AM1707
      • You need to change the code to according to your own board configure (SDRAM and flash driver) and recompile the executable program.
    • CCS flash writer can be found in the PSP release (eg. DaVinci-PSP-SDK-\src\utils\)
      • Contains flash writers for NOR/NAND/SPI-FLASH/MMCSD. These writers can be run from withing CCS to write programs to flash for boot.