OMAP-L138/C6748/AM1808 Hardware Debugging Guide

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General Items to Confirm/Check

  • Confirm exactly which part/package you are using
    • Which silicon revision
      • See the “Revision Identification” section of the Errata to decode the silicon revision number from the package symbolization
      • Read out the JTAG device ID register via JTAG/software
    • Which speed grade and temperature range does the part support
      • Look up via the orderable part number in the datasheet Device Nomenclature table
  • Check the latest device Errata for your silicon revision for a matching problem description
  • Check the schematics against the schematic check-list:

Electrical Issues

  • Ensure the device supply rails are within spec
    • Confirm that the supply rails are sequenced as required in section “Power Supplies” of the datasheet
    • Check that the CVDD voltage applied is sufficient for the chosen operating point
    • Probe the supply rails to verify that the supply stays within the MIN/MAX values shown in section “Recommended Operating Conditions” of the datasheet.
  • Ensure the device clocks are within spec
    • Check the main input clock
      • When using an External Clock Input
        • Measure the frequency, pulse width, transition time, and period jitter on the OSCIN clock and compare against the requirements in datasheet table “OSCIN Timing Requirements for an Externally Driven Clock”
        • Measure the output low and high voltage levels of the external clock and confirm that they are within the ranges specified in datasheet tables “Absolute Maximum Ratings Over Operating Junction Temperature Range” and “Recommended Operating Conditions”
      • When using a crystal in conjunction with the internal oscillator
        • Check the crystal datasheet to confirm that the crystal complies with the requirements listed in datasheet section “Crystal Oscillator or External Clock Input”
    • If using SATA, check that the SATA_REFCLK source complies with datasheet table “SATA Input Clock Source Requirements”
  • Ensure that the proper sequence is used to bring the device out of reset
    • Probe the RESETn input to the device to ensure that it is held low until the power supplies are stable, the OSCIN clock source is stable, and the minimum pulse width defined in datasheet table “Reset Timing Requirements” table is met.
    • Probe the Boot pins to ensure that setup/hold time with reference to the release of device RESETn meets the requirements defined in datasheet table “Reset Timing Requirements”
  • Ensure that timing has been closed on all I/O interfaces
    • Measure the I/O voltage levels (high and low) and compare against the datasheet Vih and Vil requirement
    • Probe the I/O buses to measure the clock frequencies, setup/hold times, and other timing requirements and compare against the datasheet timings
    • Measure the transition times of inputs to the device and check against the maximum limit in the datasheet “Recommended Operating Conditions” table
    • For high-speed interfaces for which no datasheet timings exist (ex. DDR, USB, and SATA), ensure that the datasheet layout guidelines are adhered to
  • Make sure the junction temp of the device is within the range specified in the datasheet
    • Measure the device case temperature and then model the junction temperature at the measured power consumption

System Level Issues

  • Clocking
    • Check that the PLL output frequencies (PLLOUT) of PLL0 and PLL1 are within the range specified by datasheet table “Allowed PLL Operating Conditions”
    • Ensure that the PLL Controller registers are locked out from erroneous software writes by setting the PLLx_MASTER_LOCK bits in the CFGCHIP0/3 SYSCFG registers
    • Confirm that the internal system clocks (SYSCLKs) are below the maximum limits shown in the datasheet table “Maximum Internal Clock Frequencies at Each Voltage Operating Point”
    • If using SATA, ensure that the SATA clock receiver is powered up via the PWRDN register in the SYSCFG module
  • Ensure that the Master Priority level of the real-time sensitive masters in the system (such as LCDC) is high enough to ensure its throughput/latency requirements are met. See the “Master Priority Control” section of the Technical Reference Manual for more information.
  • Resolve underflow issues by changing master priorities and EMIF priority settings
  • Check the PINMUX0-19 registers in the SYSCFG module to verify that all required signals are assigned to device pin
  • Check the PSC Registers to ensure that all needed modules are enabled

Device Pin Issues

  • To verify that you are probing the correct device pin, reprogram that PINMUX register for that pin to put it under GPIO control. The GPIO peripheral can then be used to toggle the pin and verify connectivity. Note: ensure that there are no other ICs in the system driving the line before converting the pin to a GPIO output.
  • Confirm that the desired pull-up/down settings for each pin have been selected in the PUPD_ENA/PUPD_SEL registers in the SYSCFG module

Module Specific Issues

  • Async EMIF
    • Probe the control signals (CS, OE, WE) to verify that the Setup, Strobe, and Hold periods are the expected number of clock cycles
    • Set the Setup, Strobe, and Hold periods to their maximum value if data corruption is observed
      • If it improves, the previous values were likely too small and need to be recalculated to ensure setup/hold timings of the EMIF and external async device are met.
    • Increase the number of Turn Around (TA) cycles ensure that the external device has time to turn off its output buffers when performing back-to-back read/writes.
    • Probe the data and OW/WE signals to ensure that datasheet setup/hold times are met for both the device and connected memories
    • If the WAIT pin is used, check to make sure that the AT bit in the INTRAW was not set in response to a wait timeout.
      • If the AT bit is set, increase the wait timeout time in the MAX_EXT_WAIT field of the AWCC register.
    • Check to make sure the A and BA address pins are hooked up appropriately for the desired data bus width.
      • See section “Interfacing to Asynchronous Memory” of the TRM
  • USB
    • Check USB status and settings in the CFGCHIP2 SYSCFG register
  • DDR2/mDDR
  • LCDC
    • Increase LCDC master priority in SYSCFG to prevent FIFO underruns
    • Ensure that the Palette is placed at the Frame Buffer base address
    • When using 12- and 16-BPP modes, which don’t require a Palette, a 32 byte Palette of value 4000h followed by all 0s must still be used
  • I2C
    • Make a list of the I2C addresses for every component in the system and check that no two components share the same I2C address
    • Probe I2C pin levels to verify they are being pulled high during periods of no activity
    • Probe the frequency of the I2C clock during a bus transaction and confirm that is below the datasheet max limit
    • Probe data and clock simultaneously to confirm that the expected I2C address appears on the bus and that the I2C slave generates an ACK by pulling the data line low for one cycle after each 8-bit transfer.
    • Check the I2C Interrupt Status register (ICSTR) bits to determine if an receive overrun, transmit underflow, no ACK, or arbitration-lost condition has occurred
      • Correct under/overflow issues by decreasing the latency of the processor or EDMA in responding to Transmit-data-ready and Receive-data-ready conditions
  • JTAG
    • Check the design of the JTAG circuit against the reference shown on the JTAG emulation XDS Target Connection Guide wiki:
    • Check to see whether the peripherals of interest support emulation suspend
      • Check the SUSPSRC register in the SYSCFG module to see if the peripheral’s emulation suspend function is tied to the ARM or DSP emulation halt
  • UART
    • TBD
  • SPI
    • TBD
  • VPIF
    • TBD
  • ARM Core
    • TBD
  • DSP Core
    • TBD
  • EDMA
    • TBD
  • PSC
    • TBD

Boot Issues

  • Read out the ROM version of your device and compare against the revision history in the ROM user guide
  • Read the BOOTCFG register in the SYSCFG module to view the boot pin states that were latched at reset
  • Run the OMAP-L138 debug GEL file to dump the state of the system
    • Check the state of PSC registers to determine that state of each module

Power Consumption Issues

  • The LCDK includes power measurement resistors that can be probed to observe device power consumption under the desired software load
  • The EVM has a power consumption daughtercard that can be plugged into observe device power consumption under the desired software load
  • The OMAP-L138 power spreadsheet can be configured to model any desired software load and produce a power estimate