OMAP-L138 LCDK Schematic Companion

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The table below is a companion tool to be used when referencing the OMAP-L138 LCDK schematics.  The Notes column explains why a specific component was included in the design or why that component's pins/balls were connected as shown.  The table can be sorted by the "Group" column to bring up all notes pertaining to a specific aspect of the design.

The schematics are available in the LCDK User Guide.

Sortable Schematic Companion Table

Reference Designator Doc Link Group Notes
J1
Power 5V power input jack. Alternatively, USB power can be used if system current is kept under 500mA.
U2 Link Power Overvoltage protection circuit for the 5V input. Prevents potential board damage and drives an LED when a voltage over 5.8V is applied to the power jack
D1 Link Power Voltage Regulator diode with a minimum working voltage of 5.0V
D2 Power LED to indicate an overvoltage condition on the input power jack
R270 Power The FLAGn pin of U2 is pulled up to prevent flash lighting of the LED upon application of power
R1 Power Resistor used to control the amount of current flowing through the LED to control brightness
S1 Reset Pushbutton switch used to reset OMAP-L138, TVP5147, AIC3106, LAN8710A, Leopard Imaging Header, Expansion Connector, LCD Expansion, and SATA clock oscillator
U1 Link Reset Processor Supervisory Circuit that holds the board in reset when the 3.3V supply is below 2.93V or when button S1 is pressed.
S2 Buttons User button connected to processor GPIO bank 2, signal 4
S3 User User button connected to processor GPIO bank 2, signal 5
D3 Power LED used to indicate 5V is connected to the board
U3 Link Power Power Management IC that takes in 5V and generates regulated 3.3V, 1.8V, and 1.3V outputs for use by all board components
R4 Power Low-resistance sense resistor used to measure 3.3V current consumption via header JP3.  Measure the voltage across JP3 and divide by 0.05 to estimate the 3.3V current in Amps.
R2 Power Low-resistance sense resistor used to measure 1.8V current consumption via header JP2. Measure the voltage across JP2 and divide by 0.05 to estimate the 1.8V current in Amps.
R5 Power Low-resistance sense resistor used to measure 1.3V current consumption via header JP4. Measure the voltage across JP4 and divide by 0.05 to estimate the 1.3V current in Amps.
R6, R8 Power These resistors set the 1.3V output of the TPS650250 via this formula.  VDCDC3 = 0.6V * (R6 + R8) / R8
Q1, Q3 Link Power Power Sequencing Transistors used to enable VDCDC2 output (1.8V) of the TPS650250 when the 1.3V suppy reaches the Q4 saturation voltage of 0.65-0.95V
Q2, Q4 Link Power Power Sequencing Transistors used to enable VDCDC1 output (3.3V) of the TPS650250 when the 1.8V suppy reaches the Q4 saturation voltage of 0.65-0.95V
U4, U5, U6 Link
Link
Link
Power Power switches that either source 5V VBUS to the USB connector J2 or use 5V VBUS from the USB connector to power the the LCDK, depending on the state of the processor pin USB_DRVVBUSn.
BH1 Power Holes to install a 1.2V battery circuit for powering the processor's Real Time Clock (RTC) while the rest of the processor is shut down.  Resistor R29 should be depopulated when a battery circuit is installed to prevent shorting the 1.3V supply and the battery together.
U8 Link UART USB UART chip that converts the processor's UART2 interface into USB format for connecting to a PC for debug.  The interface will appear as a standard COM port in a PC terminal application such as Hyperterminal.
U9 Link Clocking CDCM61001 Clock synthesizer for generating the low-jitter 100MHz clock required to operate the processor's SATA interface. This generator was chosen to comply with the clock requirements listed in section "SATA Interface Clock Source requirements" of the processor datasheet.
J4 SD microSD (uSD) connector with card detect (CD) signal connected to GPIO bank 4, signal 0 of the processor
Y2 Link Clocking 32.768 kHz crystal used by the processors RTC oscillator
Y3 Link Clocking 24MHz, 3.3V external oscillator that provides the processor's main input clock.  The output on pin 3 is passed through a voltage divider made up of R43 and R264 to convert the clock to 1.3V (same as CVDD) as required in Section 4.1 of the datasheet.
J6 JTAG/EMU 14-pin JTAG header for connecting a 3.3V emulation pod.  The hookup of J6 complies with http://processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide#Single_Device_Non-buffered_Configuration since all JTAG trace lengths are less than 6 inches.
J5 USB USB Host A connector for plugging in peripherals to the processor's USB1.1 port.
U11 Link Reset AND gate that combines the power monitor reset (BRD_RSTn) with the processor's reset output (RSTOUTn).  This ensures that the TVP5147, AIC3106, LAN8710A, Leopard Imaging Header, Expansion Connector, LCD Expansion, and SATA clock oscillator remain in reset until the processor comes out of reset.
Q6A Link User Driver for LED D4 which is connected to the processor's GPIO bank 6, signal 13
Q6B Link User Driver for LED D5 which is connected to the processor's GPIO bank 6, signal 12
SW1 Boot / User Switch bank with switches 1-4 mapping to processor pins BOOT4-BOOT1 respectively.  BOOT0 and BOOT5-7 are pulled down by default, but can be pulled up by populating R252, R261-264 and depopulating R82-85.  Switches 4-8 are User switches connected to the processor's GPIO bank 0, signals 1-4.  Placing the swithes in the ON position pulls the signals low, while turning OFF the switches pulls the signals high.
J7 SATA SATA Header
U14 Link Video BUS Transceiver for converting the processor's LCDC data signals from 3.3V to 1.8V for compatibility with the THS8135 Video DAC and LCD daughterboards.
U13 Link Video THS8135 video DAC for driving the VGA connector J8.  The RGB5:6:5 data is converted to RGB10:10:10 by replicating the upper R, G, and B bits on the lower portion of the 10=bit bus.  This technique is used to optimize dynamic range and linearity.
J8 Video VGA output connector.  Inputs: RGB analog signals from the THS8135, H/VSYNC signals from the voltage converter U15, I2C signals from voltage converter U16, and 5V.  The 5V input is used to power the I2C circuit inside of a monitor than can be used to read out supported resolutions.
U16 Link Video I2C Voltage converter to provide a 5V I2C to the VGA connector.
U15 Link Video Voltage converter to provide 5V H/VSYNC signals to the VGA connector
U12 Link Video BUS Transceiver for converting the processor's LCDC pixel clock and enable signals from 3.3V to 1.8V for compatibility with the THS8135 Video DAC and LCD daughterboards.
U17 Link DDR DDR2 memory chip.  See the processor datasheet for DDR2 schematic guidelines.
U18 Link NAND 1Gbit NAND flash with 16-bit data bus which uses EMIFA chip select 3 (CS3) to enable the flash, WAIT0 input to receive interrupts from the flash, and uses EMIFA address lines A1 and A2 to control ALE and CLE.  See the NAND flash section of the processor's TRM for the memory mapped addresses that are compatible with this hookup.
U21 Link Video TVP5147 Video Decoder for composite input video.  Input 2 is used for brining in the analog video, and the upper 8 bits of the output digital video is connected to the processor's 8-bit VPIF interface.  The decoder is controlled by the processor via the processor's I2C0 interface.
U27 Link Video A buffer to prevent the TVP5147M1 DATACLK from driving the processor's VPIF_CLKIN0 signal during board reset.  This was included since the TVP5147M1 drives this pin during reset and could create a drive conflict with a plugged-in Leopard Imaging camera module.
Y4 Link Video 27MHz crystal for use by the TVP5147M1's internal oscillator.
J9 Video Composite video input connector for bringing in NTSC/PAL video.  A filter circuit is put on this input in the form of FB11, C163, R273, C164, C162, and C165.
U22 Link Audio AIC3106 Audio Codec with stereo Line In, Line Out, and Microphone inputs/outputs and connected to the processor's McASP interface .  The captured audio is fed to the processor's McASP serializer # 13 and the output audio is sourced from the processor's McASP serializer # 14.  The codec BCLK is connected to the McASP ACLKX pin, and the WCLK is connected to the McASP AFSX pin.  The codec's master clock is source from a 24MHz oscillator Y5.
J11 Audio Microphone Input Jack with a bias voltage for unpowered microphones and a detection circuit.  The input is fed to the MIC input of the AIC3106 codec U22.
Y5 Link Audio 24MHz clock generator that provides the AIC3106 with its master clock MCLK input.  Other clock frequencies can be used as described in the "AUDIO CLOCK GENERATION" section of the AIC3106 datasheet.  This is useful when alternative clocks may already be available in the system and can be reused.
U23 Link Network 10/100 Ethernet PHY LAN8710A connected to the processor's EMAC MII and MDIO interfaces.  The PHY address is assigned to 0x7 via pull-ups on the PHYAD2:0 pins, and the PHY mode is set to "All capable. Auto-negotiation enabled."  The PHY's interrupt pin is connected to the processor's GPIO bank 0, signal 15.
Y6 Network 25MHz crystal for use by the Ethernet PHY's internal oscialltor.  If a 25 MHz clock source already exists in a system, it can be used in place of this crystal.
J13 Network Ethernet RJ-45 jack with built-in magnetics and connected to the LAN8710A PHY.  The jack's green light is connected to the PHY's LED2, and the yellow light is connected to the PHY's LED1. The MAC address assigned to the board is printed on a sticker that is applied to the top of this connector.
Q5A Link User Driver for LED D6 which is connected to the processor's GPIO bank 2, signal 12
Q5B Link User Driver for LED D7 which is connected to the processor's GPIO bank 0, signal 9
J14 Expansion General Expansion connector containing EMIFA signals.
J15 Expansion General Expansion connector containing MMCSD1, SPI, UART, I2C, McASP signals.
P1, P2 Video LCD Expansion connectors the provide the processor's LCDC signals for use by a touch-screen LCD daughterboard.
U28 Video Voltage converter for converting the interrupt from an expansion touchscreen LCD from 1.8V to 3.3V before connecting to the processor's GPIO bank 2, signal 6
U24 Link Video Voltage converter for converting the processor's LCDC H/VSYNC signals from 3.3V to 1.8V before sending them to the expansion touchscreen LCD connector
R192-97 ID Pull resistors who's population option conveys the BOARD ID to the processor's GPIO bank 6, signals 9-11. The revision of the board can also be found written on the silkscreen on the top edge of the board. The board serial number is placed on a sticker on the underside of the board.
J16 Video Expansion connector for interfacing with Leopard Imaging camera modules equipped with the 36-pin ZIF connector. It connects to the processor's VPIF input port and I2C0 or SPI1 ports.
U25 Link Video Voltage converted for converting the I2C0 interface from 3.3V to 1.8V before sending to the LCD expansion header.
U26 Link Fingerprint Authentec AES850 swipe fingerprint sensor / trackpad. The processor can talk to the AES850 via either SPI or I2C based on the resister populations R200-209. The interrupt from AES850 is routed to the processor's GPIO bank 6, signal 8.