Please note as of Wednesday, August 15th, 2018 this wiki has been set to read only. If you are a TI Employee and require Edit ability please contact x0211426 from the company directory.
OMAP-L13x / C674x / AM1x Schematic Review Checklist
- 1 Introduction
- 2 BGA PCB Design
- 3 Power Management Solutions
- 4 Recommendations Specific to OMAP-L1x / TMS320C674x / AM1x
- 4.1 EVM vs Datasheet
- 4.2 Critical Connections
- 4.3 Peripherals
- 4.4 If not used
- 5 General Recommendations
- 5.1 Before you begin
- 5.2 Critical Connections
- 5.3 Peripherals
- 5.4 Debug Considerations
- 5.5 Other
- 5.6 References
This article applies to the following devices:
- TMS320C6748 / TMS320C6746 / TMS320C6742
- TMS320C6747 / TMS320C6745 / TMS320C6743
- AM1810 / AM1808 / AM1806 / AM1802
- AM1707 / AM1705
For OMAP-L1x DSP + ARM9 based processors, please refer to this link: [OMAP-L1x based processors].
For C6000 power optimized DSPs, please refer to this link: [C6x DSPs].
For ARM9 based processors, please refer to this link: [ARM9 processors].
The following table is not an all encompassing feature list. It is intended to show differences between the devices in order to know which sections of this article apply to your specific device. Features common to all devices such as McASP, USB, Timers, eCAP, ePWM, etc are not shown. The chart is color coded to emphasize the groups of devices that are pin-for-pin compatible, e.g. migration from c6748 to OMAP-L138 is a drop-in replacement requiring no hardware changes.
| OMAP-L132 (ZWT only)
| AM1810 (ZWT only)
| AM1802 (ZWT only)
||NO||NO||YES||YES||YES||NO||1||0||256-ball BGA (ZKB)|
|| 176-pin HLQFP (PTP) |
BGA PCB Design
- C6x DSP uses 0.65mm-pitch ZCE, 0.80mm-pitch ZWT, and 176-pin HLQFP (PTP) package. Please refer to this link for BGA PCB design guideline: [BGA PCB Design Guideline].
Power Management Solutions
- For TT power management solutions, please refer to the TI power management webpage: [TI Power Management Solutions]. In addition, WEBBENCH designer tools provide a visual interfaces that deliver a complete power application in seconds [WEBBENCH].
Recommendations Specific to OMAP-L1x / TMS320C674x / AM1x
EVM vs Datasheet
- In case of any discrepancy between the TI EVMs and the device datasheet, always follow the datasheet. Despite the designer's best efforts, the EVMs may contain errors which may still function but are not completely aligned with the datasheet specification. Therefore the EVM designs should not be considered as reference designs to be blindly reused.
- Check that the correct voltages are applied to the correct power pins on the chip and that the required current can be supplied.
- Zero ohm resistors inline with core and other power sections of the board are recommended for initial PCB builds if the user wants to measure power. The user can then remove the 0 ohm resistor and measure power if required.
- Check that power comes up in the correct sequence.
- The DVDD18 I/O supply must always be connected, even when the dual-voltage I/Os are supplied with 3.3V.
- RTC_CVDD may be connected to CVDD if no battery is used, even when using the 1.3V core OPP.
- Verify that the PLL0 and PLL1 supplies follow the filtering requirements shown in the datasheet. Each PLL must have its own filter in order to guarantee noise immunity.
- If supplying an external clock to the OSCIN pin make sure it is of the correct amplitude -- 1.2V.
- Clock sources
- RTC oscillator @ 32KHZ
- CLKIN pin @ 12MHz (for bootloader)
- Do not need RTC oscillator if...
- Not sourcing external clock from RTC XO
- Do not need RTC clock
- Do not need RTC-only mode
- Do not need Power on Reset POWERGOOD signal (RESET asserted externally)
The CLKOUT clock output is provided as PLL observation clock, and is provided for test and debug purposes only. It should not be used as a synchronous clock for any of the peripheral interfaces because it was not timing closed to any other signals. This clock output also was not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance is dependent on many system variables, and also influenced by other unpredictable contributors to jitter performance such as application specific noise and cross talk into the clock circuit. There is no characterization data for the jitter performance for CLKOUT.
- Make sure TRST is pulled low on the board during power up. A POR (RESET and TRST low) is required to initialize the internal logic and correctly boot up the device for the first time.
- Use external pull resistors rather than tying boot pins to ground or VDD.
- For OMAPL137/C6747 devices, the UART boot mode will be supported only if the input clock is 24 MHz.
- Include pullup resistors on EMU0 and EMU1 pins.
- Please follow these recommendations when designing your JTAG interface.
- The XDS Connector Design Checklist provides a convenient list of recommendations per XDS/JTAG signal.
- You might also want to look at the article JTAG Connectors when deciding which header to put on the board. Double-check the pin-out!
Digital GND, Analog GND, Local GND
- Digital GNDs: VSS, SATA_VSS
- Analog GNDs: OSCVSS, PLL0_VSSA, and PLL1_VSSA
- Local GNDs:
- Must not be connect local GND to the board ground unless otherwise stated (ie. USB not used - See [#If USB is not used])
- RTC_VSS - Local ground for RTC oscillator (must not be connected to the board ground)
- OSCVSS - Local ground for oscillator
- PLL0_VSSA and PLL1_VSSA - local ground for PLL
- Put pullups on the UART_TXD pins. During reset, these pins are internally pulled low, and host software may interpret this as sending null characters unintentionally.
- This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:
- TX ---> RX
- RX <--- TX
- The RMII reference clock (RMII_MHZ_50_CLK) must have a jitter tolerance of 50 ppm or less
- Typically weak (~51K) pull ups on all MMC/SD lines are helpful.
USB0 (USB 2.0 OTG)
|HS Host||FS Host||LS Host||HS Device||FS Device||LS Device||OTG A Device||OTG B Device|
|USB0_DM||Series or pull resistor needed?||No||No||No||No||No||No||No||No|
|USB0_DP||Series or pull resistor required?||No||No||No||No||No||No||No||No|
|USB0_ID||Connect to...||Ground||Ground||Ground||Floating||Floating||Floating||Direct to cable||Direct to cable|
|USB0_VBUS||Connect to...||Power supply & connector||Power supply & connector||Power supply & connector||Connector||Connector||Connector||Power supply & connector||Connector|
|USB0_REFCLKIN||Recommended frequencies...|| |
|USB0_VDDA12||Bypass cap value|| |
|USB0_CVDD||Connect to...|| |
1.2V (1.32V max)
USB Board Design Guideline
- Check that the USB hardware design guidelines will be followed
In the case which USB PHY is powered off while still connected to a powered-on host
- When USB PHY is powered off while still connected to a powered-on host, the customer would notice leakage voltage on the 3.3V supply. This is due to the fact there is a path between VBUS and 3.3V supply rail, that when 3.3V is not applied to the power rail, allow voltage to be leaked from powered VBUS to the 3.3V supply rail. If USB PHY remains to be powered off for an indefinite time, then there is a risk of long-term fatigue on the PHY internal circuitry.
- TI therefore recommends customers employing this use-case to isolate the input USB0_VBUS from the VBUS during device being in power-off state until the device eventually is powered up, by implementing a discrete load switch such as the http://www.ti.com/product/tps22913c. Below shows the overall connection diagram:
- For DSP that supports OTG Host/Device Mode
- For DSP that supports USB Device Only Mode
USB1 (USB 1.1 OHCI)
- No external pull resistors are required for the DM/DP pins.
- Connect USB_CVDD to 1.2V (1.32V max)
- Check that chip selects go to the proper memory for a correct memory map.
- For booting from NAND devices, make sure EMA_CS is used.
- For booting from NAND devices, make sure that the NAND device will work with the boot loader if non ONFI compliant.
- EMIFA does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read, therefore make sure that the NAND flash selected for boot will work with the EMIFA NAND controller. Additionally check out the following link
- For booting from NOR devices, make sure EMA_CS is used.
- Weak pullups are recommended on chip selects.
- Verify address pins are connected correctly according to the following wiki: Connecting NOR Flash to OMAP-L138
- No parallel terminator is allowed on CLKP/CLKN pins
- If terminators are used, the DDR2/mDDR drive strength should be set to full strength. Otherwise, the drive strength should be set to half strength.
- No pullups or stubs are allowed on any DDR pins
- For DQS and D net class, the routes are point to point. Skew matching across bytes is not needed nor recommended. However, recommending skew between the two classes does not exceed 25mil
- Clock and DQS net class trace length need to be rouoted such that the skew between the two net classes need to meet tDQSS timing parameter
- For booting with SPI EEPROM or Flash devices, make sure SPIx_CS is used.
- Keep in mind that the transmit bit clock, ACLKX, can only be driven externally from the AHCLKX pin or AUXCLK. It cannot be sourced from the AHCLKR pin. Check McASP user guide for clock sourcing diagrams.
Audio (if present)
- Check for good filtering on audio power.
- Audio ground: Audio ground should be of the single point ground type. This is accomplished by separating (and using different symbols for) digital and analog grounds on the schematic and then connecting them together with a 0 ohm resistor or ferrite bead in the schematic. In the layout this will ensure that all audio grounds are connected to digital ground at only one point, thereby reducing the chance of ground loops.
If not used
Please see the Unused Pin Configurations section of the data manual. It is Section 3.8 for AM18xx and TMS320C674x devices, and it is Section 3.9 for OMAP-L13x devices.
THIS SECTION IS TRANSCLUDED FROM HARDWARE DESIGN CHECKLIST. ONLY INFO GENERIC TO ALL DEVICES BELONGS HERE SINCE IT APPEARS IN ALL SCHEMATIC CHECKLISTS.
Before you begin
Make sure you have the latest version of documentation, especially the data sheet and silicon errata.
TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important.
TIP: - on each ti.com device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata.
Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling.
PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply.
Are all requirements being met in terms of the order, delays, etc. of the power supplies?
Make sure your input clock/crystal meets the data sheet requirements. For example:
OSC Internal Oscillator Clock source
The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components.
In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality:
Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms
However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs.
Please refer the below application note for calculation of Rs and RBais values:
Please refer the application note for the calculation of Rs and RBais values Crystek Application notes
Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable!
A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets.
Also, you might want to have a reset button on your board as it can be helpful for development.
Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately.
DDR2 Routing Checklist
External Memory Interface (NOR/async)
The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly.
This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:
This is something often done incorrectly which can severely impact your ability to develop code!
For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well.
Voltage Level Changes
Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later.
Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction.
For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption.
The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools.
The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board.
This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.