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OMAP-L13x / C674x / AM1x Schematic Review Checklist

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Introduction

This article applies to the following devices:


For OMAP-L1x DSP + ARM9 based processors, please refer to this link: [OMAP-L1x based processors].

For C6000 power optimized DSPs, please refer to this link: [C6x DSPs].

For ARM9 based processors, please refer to this link: [ARM9 processors].


The following table is not an all encompassing feature list.  It is intended to show differences between the devices in order to know which sections of this article apply to your specific device. Features common to all devices such as McASP, USB, Timers, eCAP, ePWM, etc are not shown. The chart is color coded to emphasize the groups of devices that are pin-for-pin compatible, e.g. migration from c6748 to OMAP-L138 is a drop-in replacement requiring no hardware changes.


ARM926
674x
SATA SDRAM
mDDR/DDR2 UPP LCD EMAC HPI VPIF MMC/SD McBSP Package
OMAP-L138
YES
YES
YES 16-bit
16-bit
YES YES YES YES YES 2 2


361-ball NFBGA

  • 0.65mm-pitch ZCE
  • 0.80mm-pitch ZWT
OMAP-L132 (ZWT only)
YES
YES
NO 16-bit
16-bit
NO NO YES NO NO 2 2
TMS320C6748
NO
YES
YES 16-bit
16-bit
YES YES YES YES YES 2 2
TMS320C6746
NO
YES
NO 16-bit
16-bit
YES NO YES YES YES 2 2
TMS320C6742
NO
YES
NO 16-bit
16-bit
NO NO NO YES NO 0 1
AM1810 (ZWT only)
YES
NO
YES
16-bit
16-bit
YES
YES
YES
YES
YES
2
2
AM1808
YES
NO
YES 16-bit
16-bit
YES YES YES YES YES 2 2
AM1806
YES
NO
NO 16-bit
16-bit
YES YES NO YES YES 2 2
AM1802 (ZWT only)
YES
NO
NO
16-bit
16-bit
NO
NO
YES
NO
NO
1
0
OMAP-L137
YES
YES
NO 32-bit
NO NO YES YES YES NO 1 0 256-ball BGA (ZKB)
TMS320C6747
NO
YES
NO 32-bit
NO NO YES YES YES NO 1 0
AM1707
YES
NO
NO 32-bit
NO NO YES YES YES NO 1 0
TMS320C6743ZKB
NO
YES
NO 32-bit
NO NO NO YES NO NO 1 0
TMS320C6743PTP
NO
YES
NO
16-bit
NO
NO
NO
YES
NO
NO
1
0
176-pin HLQFP (PTP)
TMS320C6745
NO
YES
NO 16-bit
NO NO NO YES NO NO 1 0
AM1705
YES
NO
NO 16-bit
NO NO NO YES NO NO 1 0





BGA PCB Design

  • C6x DSP uses 0.65mm-pitch ZCE, 0.80mm-pitch ZWT, and 176-pin HLQFP (PTP) package. Please refer to this link for BGA PCB design guideline: [BGA PCB Design Guideline].

Power Management Solutions

  • For TT power management solutions, please refer to the TI power management webpage: [TI Power Management Solutions]. In addition, WEBBENCH designer tools provide a visual interfaces that deliver a complete power application in seconds [WEBBENCH].


Recommendations Specific to OMAP-L1x / TMS320C674x / AM1x

EVM vs Datasheet

  • In case of any discrepancy between the TI EVMs and the device datasheet, always follow the datasheet. Despite the designer's best efforts, the EVMs may contain errors which may still function but are not completely aligned with the datasheet specification. Therefore the EVM designs should not be considered as reference designs to be blindly reused.

Critical Connections

Power

  • Check that the correct voltages are applied to the correct power pins on the chip and that the required current can be supplied.
  • Zero ohm resistors inline with core and other power sections of the board are recommended for initial PCB builds if the user wants to measure power. The user can then remove the 0 ohm resistor and measure power if required.
  • Check that power comes up in the correct sequence.
  • The DVDD18 I/O supply must always be connected, even when the dual-voltage I/Os are supplied with 3.3V.
  • RTC_CVDD may be connected to CVDD if no battery is used, even when using the 1.3V core OPP.
  • Verify that the PLL0 and PLL1 supplies follow the filtering requirements shown in the datasheet. Each PLL must have its own filter in order to guarantee noise immunity.

Clocking

  • If supplying an external clock to the OSCIN pin make sure it is of the correct amplitude -- 1.2V.
  • Clock sources
    • RTC oscillator @ 32KHZ
    • CLKIN pin @ 12MHz (for bootloader)
  • Do not need RTC oscillator if...
    • Not sourcing external clock from RTC XO
    • Do not need RTC clock
    • Do not need RTC-only mode
    • Do not need Power on Reset POWERGOOD signal (RESET asserted externally)
  • CLKOUT

The CLKOUT clock output is provided as PLL observation clock, and is provided for test and debug purposes only. It should not be used as a synchronous clock for any of the peripheral interfaces because it was not timing closed to any other signals. This clock output also was not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance is dependent on many system variables, and also influenced by other unpredictable contributors to jitter performance such as application specific noise and cross talk into the clock circuit. There is no characterization data for the jitter performance for CLKOUT.

Reset

  • Make sure TRST is pulled low on the board during power up. A POR (RESET and TRST low) is required to initialize the internal logic and correctly boot up the device for the first time.

Boot

  • Use external pull resistors rather than tying boot pins to ground or VDD.
  • For OMAPL137/C6747 devices, the UART boot mode will be supported only if the input clock is 24 MHz.




Debug

  • Include pullup resistors on EMU0 and EMU1 pins.

JTAG/Emulation


Digital GND, Analog GND, Local GND

  • Digital GNDs: VSS, SATA_VSS
  • Analog GNDs: OSCVSS, PLL0_VSSA, and PLL1_VSSA
  • Local GNDs:
    • Must not be connect local GND to the board ground unless otherwise stated (ie. USB not used - See [#If USB is not used])
    • RTC_VSS - Local ground for RTC oscillator (must not be connected to the board ground)
    • OSCVSS - Local ground for oscillator
    • PLL0_VSSA and PLL1_VSSA - local ground for PLL

Peripherals

UART

  • Put pullups on the UART_TXD pins. During reset, these pins are internally pulled low, and host software may interpret this as sending null characters unintentionally.
  • This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:
  • TX ---> RX
  • RX <--- TX

EMAC

  • The RMII reference clock (RMII_MHZ_50_CLK) must have a jitter tolerance of 50 ppm or less

MMC/SD

  • Typically weak (~51K) pull ups on all MMC/SD lines are helpful.

USB0 (USB 2.0 OTG)

Pin Question Operating Mode
HS Host FS Host LS Host HS Device FS Device LS Device OTG A Device OTG B Device
USB0_DM Series or pull resistor needed? No No No No No No No No
USB0_DP Series or pull resistor required? No No No No No No No No
USB0_VDDA33 Connect to... 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
USB0_ID Connect to... Ground Ground Ground Floating Floating Floating Direct to cable Direct to cable
USB0_VBUS Connect to... Power supply & connector Power supply & connector Power supply & connector Connector Connector Connector Power supply & connector Connector
USB0_REFCLKIN Recommended frequencies...
12,24,48,19.2,38.4,13,26,20,40 MHz
USB0_VDDA18 Connect to... 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
USB0_VDDA12 Bypass cap value
0.22uF
USB0_CVDD Connect to...
1.2V (1.32V max)

USB Board Design Guideline

In the case which USB PHY is powered off while still connected to a powered-on host

  • When USB PHY is powered off while still connected to a powered-on host, the customer would notice leakage voltage on the 3.3V supply. This is due to the fact there is a path between VBUS and 3.3V supply rail, that when 3.3V is not applied to the power rail, allow voltage to be leaked from powered VBUS to the 3.3V supply rail. If USB PHY remains to be powered off for an indefinite time, then there is a risk of long-term fatigue on the PHY internal circuitry.
  • TI therefore recommends customers employing this use-case to isolate the input USB0_VBUS from the VBUS during device being in power-off state until the device eventually is powered up, by implementing a discrete load switch such as the http://www.ti.com/product/tps22913c. Below shows the overall connection diagram:
  • For DSP that supports OTG Host/Device Mode

USB OTG Host Device Mode.JPG

  • For DSP that supports USB Device Only Mode

USB Device Mode Only.JPG

USB1 (USB 1.1 OHCI)

  • No external pull resistors are required for the DM/DP pins.
  • Connect USB_CVDD to 1.2V (1.32V max)

EMIF

  • Check that chip selects go to the proper memory for a correct memory map.
  • For booting from NAND devices, make sure EMA_CS[3] is used.
  • For booting from NAND devices, make sure that the NAND device will work with the boot loader if non ONFI compliant.
  • EMIFA does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read, therefore make sure that the NAND flash selected for boot will work with the EMIFA NAND controller.  Additionally check out the following link
  • For booting from NOR devices, make sure EMA_CS[2] is used.
  • Weak pullups are recommended on chip selects.
  • Verify address pins are connected correctly according to the following wiki: Connecting NOR Flash to OMAP-L138

DDR2/mDDR

  • No parallel terminator is allowed on CLKP/CLKN pins
  • If terminators are used, the DDR2/mDDR drive strength should be set to full strength. Otherwise, the drive strength should be set to half strength.
  • No pullups or stubs are allowed on any DDR pins
  • For DQS and D net class, the routes are point to point. Skew matching across bytes is not needed nor recommended. However, recommending skew between the two classes does not exceed 25mil
  • Clock and DQS net class trace length need to be rouoted such that the skew between the two net classes need to meet tDQSS timing parameter

SPI

  • For booting with SPI EEPROM or Flash devices, make sure SPIx_CS[0] is used.

McASP

  • Keep in mind that the transmit bit clock, ACLKX, can only be driven externally from the AHCLKX pin or AUXCLK. It cannot be sourced from the AHCLKR pin. Check McASP user guide for clock sourcing diagrams.

Audio (if present)

  • Check for good filtering on audio power.
  • Audio ground: Audio ground should be of the single point ground type. This is accomplished by separating (and using different symbols for) digital and analog grounds on the schematic and then connecting them together with a 0 ohm resistor or ferrite bead in the schematic. In the layout this will ensure that all audio grounds are connected to digital ground at only one point, thereby reducing the chance of ground loops.

If not used

Please see the Unused Pin Configurations section of the data manual. It is Section 3.8 for AM18xx and TMS320C674x devices, and it is Section 3.9 for OMAP-L13x devices.

USB

NOTE

The data manual recommends connecting USB0_VDDA12 to a 0.22uF capacitor even when neither USB port is being used. That differs from an earlier recommendation to leave USB0_VDDA12 as a no-connect in the case where neither USB port is used. That connection is not expected to be problematic for existing designs, but the recommendation moving forward is to always populate the 0.22uF capacitor. This is discussed in this post.

General Recommendations

THIS SECTION IS TRANSCLUDED FROM HARDWARE DESIGN CHECKLIST. ONLY INFO GENERIC TO ALL DEVICES BELONGS HERE SINCE IT APPEARS IN ALL SCHEMATIC CHECKLISTS.


As you are creating the schematics for your project here are a few things to consider.

Before you begin

Documentation

Make sure you have the latest version of documentation, especially the data sheet and silicon errata.

TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important.

TIP: - on each ti.com device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata.

Pin out

  • Have you verified that your pin labels correspond to the correct pin numbers?
  • Have you verified that the power pins are connected to the correct supply rails?
  • Pullups/Pulldowns:
Internal pull-up/pull-down resistors are implemented with weak transistors. As the voltage present on the I/O pin varies the relative gate voltage to this weak transistor changes which will cause the effective pull-up/pull-down resistance to change. Therefore, internal resistors do not have a linear response like external resistors. The non-linearity along with process voltage and temperature variations require internal pull-up/pull-down resistors to be specified with a wide range of resistance or current sourcing/sinking.
The input current without a pull-up or pull-down turned on defines the input leakage without any current from internal pull resistors. The input current with a pull-up or pull-down turned on defines a combination of input leakage current and current required to force the internal pull resistors to the opposite voltage rail. For example, if an internal pull-up is turned on the value shown represents the total current required to pull the input to VSS.
When deciding what value of external resistor to use, you must consider the worst case combination of all internal leakage paths of all devices connected to a signal and make sure the external resistor is able to force these internal leakage paths to a potential greater than Vih min, or less than Vil max.

Critical Connections

Decoupling Capacitors

Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling.

PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply.

Refer to General Hardware Design/ BGA PCB Design/BGA Decoupling Wiki

Power Sequencing

Are all requirements being met in terms of the order, delays, etc. of the power supplies?

Clocking

Make sure your input clock/crystal meets the data sheet requirements. For example:

  • Frequency
  • ESR for crystal
  • Load capacitance meets both the crystal’s and processor’s requirements
  • Crystal and caps placed physically close to processor
  • Double check proper voltage level for clock (some devices will use core voltage, others I/O voltage).
  • If there are any PLL configuration pins make sure they are set such that the resulting frequency is within device spec. Also, having alternate population options for those PLL pins could be handy.

OSC Internal Oscillator Clock source

The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components.

  • OSC Crystal Circuit Schematics

Clockckt v2.jpg

In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality:

Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms

However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs.

Please refer the below application note for calculation of Rs and RBais values:

Please refer the application note for the calculation of Rs and RBais values Crystek Application notes


Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the OMAPL1x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.

Reset

Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable!

A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets.

Also, you might want to have a reset button on your board as it can be helpful for development.

Boot modes

  • Double check that the boot configuration pins are set to the correct option.
  • It's highly recommended to have some population options to be able to easily change the reset mode. This can be handy in a variety of circumstances. For example, if you were doing a NOR flash boot and you ever accidentally put in some bad code you might end up in a scenario where you can't connect to the device with emulator because it's in a bad state, and you can't reprogram the flash as a result! Having an alternate boot mode can be a life saver!
  • Read carefully the initialization section in the Technical Reference Manual of your processor. We may have to deal with important information that can change your design. Look for which chip select is used by default, default clock setups, bus widths, wait states, supported booting devices, initial fetch address and interrupt vector addresses, default memory map and so on.
  • CAUTION: Be careful if anything is hooked up to these pins (i.e. if the pins are have multiple uses such as GPIO or other peripherals). You must make sure that the boot pins are at the proper levels when power-on reset occurs such that the correct values are latched in order for the device to boot correctly!

Pin Muxing

Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately.

Peripherals

USB

  • Check that there are no unnecessary USB_DM or USB_DP connections that would form stubs.
  • Check that there is nothing on the DP/DM lines (except for possibly a USB 2.0 certified surge suppressor)
  • USB supports hot insertion and removal so it is very vulnerable to ESD resulting from this. External ESD protection like the TPD2E001 or TPD3E001 is recommended. For USB OTG the recommended ESD protection is the TPD4S012. Any USB 2.0 certified ESD protection chip is acceptable as long as the USB PCB routing guidelines are followed.

DDR2 Routing Checklist

DDR2/mDDR Routing Checklist

External Memory Interface (NOR/async)

The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly.

I2C

  • ~5K pull ups on both lines (only one set, or two sets of 10K pull ups) are recommended
  • Make sure all devices on a given I2C bus have unique addresses (often this is configurable through a pin to enable multiple of the same device)

UART

This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:

  • TX ---> RX
  • RX <--- TX

Debug Considerations

JTAG/Emulation

This is something often done incorrectly which can severely impact your ability to develop code!

Signal Visibility

For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well.

Other

Voltage Level Changes

Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later.

Signal Terminations

Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction.

For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption.

Ground Symbols

The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools.

Power Symbols

The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board.

References

This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.