WL127x Hardware Design Guide

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This document describes hardware specifications for those modules that are based on the WiLink™ 6.0 system solution.

Literature Number: SPRAB95

January 2010


WiLink™ 6.0 is a Wireless Local Area Network (WLAN) chipset. This application note describes the hardware specifications for those modules that are based on this system solution.

This document is intended to provide a brief overview of the WL6.0-based hardware solution. The OMAP3530 Evaluation Module (EVM) and the LSR WLAN module are used for the purpose of example. This documentation equally applies to the AM3715/DM3730 EVM.

For system design, it is strongly recommended to use the full range of datasheets and application notes available for the EVM and the LSR module.

WiLink 6.0-based (1271/3) Module Solution Overview

WLAN Configuration

The WiLink (WL) 6.0 solution consists of:

  • SMPS: Switching-mode power source that provides a 1.8V supply for the 1271. This component enables the module to be directly connected to the battery voltage. The SMPS converts the battery voltage to the 1.8V supply required by the 1271 device.
  • Clock Sources: There are two clock sources required – a 32KHz slow clock and a fast clock.
  • Front-end Module: A combination of PA and a switch.
  • A bandpass filter to filter out-of-band noise and interference.

Solution Hardware-Figure1.jpg

Figure 1: WL6.0 System Solution

External Interfaces

Solution Hardware-Figure2.jpg

Figure 2: Simplified Representation of External Interfaces

Note: Some signals shown in the figure above may not be exposed on some solutions.

The external interfaces to the chip can be grouped as follows:

  • WLAN host interface:
  • SDIO interface
  • WL_IRQ
  • WL_EN
  • Bluetooth (BT) interface:
  • Pin UART interface with HCI protocol
  • Bluetooth enable
  • Frequency Modulation (FM) interface: Refers specifically to the FM radio inside the device.
  • FM shares the HCI interface with Bluetooth
  • FM can also use a dedicated I2C
  • Top-level interface:
  • Power and reset
  • Clocks
  • Power supply controls
  • Debug interface

Each of these interfaces are described below.

Power On, Reset and Enable Functions

The WL1271 has three enable (EN) pins, with one for each core:

  • WL_EN
  • BT_EN
  • FM_EN

Two modes of operation are provided:

  • Each core is operated independently by asserting each EN to Logic 1. In this mode, it is possible to control each core asynchronously and independently.
  • Shared mode operation (BT and FM only are shared). WLAN is operated through WL_EN asynchronously, independent of BT and FM. Control of the FM core is performed through the BT HCI. The FM_EN signal should be connected to GND.

In shared mode, the operation of the FM Enable should be performed in the following sequence:

1 Operate BT.

2 Send an FM ON command via the HCI.

3 If FM is switched off, first send an FM_OFF command.

4 Then, send a BT_OFF command.

Failing to turn the FM core off before the BT core results in the FM remaining on.


The 1271/3 SoC contains three Interrupts (WLAN, BT and FM).

There are three different interrupt pins to control each IP separately:

  • WL_IRQ: For the SDIO/SPI Interface
  • BT_IRQ: For the SPI interface muxed on HCI_RTS
  • FM_IRQ: The I2C interface

WLAN Interface

WLAN Host Interface (SDIO)

The host can interface the WLAN with either an SDIO or SPI interface. However, only the SDIO interface is supported on TI Platforms and with the reference WLAN driver. The main reason for this is that an SPI interface supports roughly one-half the bandwidth of a four-bit SDIO interface.

The WLAN acts as a slave with the host (OMAP and so on) as the master. This means that the host generates the SDIO clock and sends commands to the WLAN, to which the WLAN responds.

Table 1: WLAN Host Interface Signals - SDIO

Signal Name Description
SPI_DIN/SDIO_CMD SDIO Command line. This is a bidirectional line. The host sends commands and the WLAN responds to these commands.
SDIO/SPI_CLK SDIO Clock line. This line is generated by the host.
SPI_DOUT/SDIO_D0 SDIO Data 0 line. This is the primary data line used in both 1-bit and 4-bit SDIO mode. This is a bidirectional line.
SDIO_D1 SDIO Data 1 line. This is one of four data lines. This line is used only in 4-bit mode. This is a bidirectional line.
SDIO_D2 SDIO Data 2 line. This is one of four data lines. This line is used only in 4-bit mode. This is a bidirectional line.
SPI_CS/SDIO_D3 SDIO Data 3 line. This is one of four data lines. This line is used only in 4- bit mode. This is a bidirectional line.

WLAN IRQ Operation (SDIO Out-of-Band Interrupt)

The WLAN IRQ is an out-of-band interrupt request line that is not defined by the SDIO standard specification. Therefore, a good understanding on how it works is required in order to work with the WL6.0-based solution.

The WLAN_IRQ line operates as follows:

1 The default state of the WLAN_IRQ prior to firmware initialization is 0.

2 During firmware initialization, the WLAN_IRQ is configured by the SDIO module. A WLAN_IRQ changes its state to 1.

3 A WLAN firmware interrupt is handled as follows:

  • The WLAN firmware creates an Interrupt-to-Host request, indicated by a 1-to-0 transition on the WLAN_IRQ line (the host must be configured as active low or falling-edge detect).
  • After the host is available, depending on the interrupt priority and other host tasks, it masks the firmware interrupt. The WLAN_IRQ line returns to 1 (a 0-to-1 transition on the WLAN_IRQ line).
  • The host reads the internal register status to determine the interrupt sources. The register is cleared after the read.
  • The host processes all the interrupts read from this register in sequence.
  • The host unmasks the firmware interrupts.

4 The host is ready to receive another interrupt from the WLAN device.

Solution Hardware-Figure3.jpg

Figure 3: WL IRQ States

Bluetooth Interface

Bluetooth uses the HCI interface to connect to the host. The 1271/3 supports both H4 (4-wire) and H5 (3-wire) interfaces. Figure 4 illustrates H4 interface connectivity.

Solution Hardware-Figure4.jpg

Figure 4: Bluetooth HCI Interface - H4 Connectivity

FM Interface

The FM primarily shares the Bluetooth HCI interface. This solution also has a dedicated I2C interface, but it is not typically used.

WLAN Operation Power Modes

The operation modes described below only serve to show the state of the signals, clocks and supplies for different modes. This document does not describe each mode in detail.

  • Shutdown mode: This is the lowest power consumption state of the device. The enable pin is pulled low for this configuration. The memory is also not retained. Therefore, a firmware download is needed to come out of this state.
  • VBAT = high/low.
  • VIO = high/low.
  • Core Ip = low.
  • The slow clock is on while the fast clock is either off or on.
  • DC2DC, FEM and SoC are not active.
  • Deep Sleep or Extreme Low Power (ELP) mode: This is also a low-power state. In this state, the memory is retained and a firmware download is required.
  • The slow clock is active and the cortex clock is gated.
  • The 1.8 V remains active, but is decreased.
  • The host can initiate or exit from this state.
  • VBAT = high/low.
  • VIO = high.
  • Core Ip = low.
  • The slow clock is on while the fast clock is either off or on.
  • DC2DC and SoC are partially active; FEM is not active.
  • Listen mode: This is a lower-power operational mode designed to save power when the WLAN is not actively sending or receiving data, but is only listening to information in 1Mbps (802.11b DSS ) mode (for example, beacons).
  • VBAT = high.
  • VIO = high.
  • All clocks are on.
  • Of the two channels (I and Q), only one channel is received (only 11b beacons).
  • DC2DC, FEM and SoC are active, but with low current.
  • STBY mode: This mode is also known as Powerdown mode. This a low-power operation mode for post processing received items. In this mode, the MAC portion is on and all other modules are shut down.
  • The hardware is on and the cortex clock is gated.
  • All clocks and voltages are on.
  • No RF operation is required.
  • DC2DC, FE and SoC are active.
  • TX mode: All chips sections are active. The PA on the FEM is also enabled.
  • VBAT = high.
  • VIO = high.
  • Core IP = high.
  • The DC2DC is in PWM mode.
  • The FEM and SoC are active.
  • RX mode: All chips sections are active.
  • VBAT = high.
  • VIO = high.
  • Core IP = high.
  • The DC2DC is in PWM mode.
  • The FEM and SoC are active.

Bluetooth and FM Operation Power Modes

The following Bluetooth and FM operation power modes are available:

  • Shutdown mode: This mode is similar to WLAN Shutdown mode.
  • Lowest power-consumption state of the device.
  • Entered by driving BT_EN low (can alternately be left floating).
  • Used when BT and FM functionalities are not required.
  • The entire device, including the internal Power Management (PM), is switched off (only power rails leakage path). There is no retention capability (to keep the memory voltage high enough to function).
  • Power-up and full initialization is required in order to exit.
  • Supplies (DC2DC and VIO) are not needed, but can be applied. Digital IOs are only defined if VIO is applied.
  • Clocks (SCLK and FREF) are not required, but can be applied (as failsafe inputs).
  • Bluetooth Deep Sleep mode:
  • Low-power state of the device.
  • Entered through a deep-sleep protocol with the host (HCILL).
  • Used when FM-only functionality is needed or when BTH is in low-power mode (for example, scan/sniff intervals).
  • Only the 32KHz portion of the device is active. The FREF cell is off. A fast clock is not required, but can be applied.
  • Core (VDD) voltage is reduced to 0.9 V. The memories array (VDDAR) voltage is reduced to 1.05 V.
  • All other PM modules are switched off, except for the KA LDOs and the DIGBGAP modules, which are in on/hibernate mode.
  • Digital logic and memories are kept in a retention state, with no need for re-initialization.
  • Bluetooth IP Active modes:
  • Standby: When the ARM and all other peripherals are active, but the device is not transmitting or receiving. BT-IP (DRPb) PM is off.
  • Idle (Big Sleep): The same as above, but the Advanced RISC Microprocessor (ARM) is idle (clock is gated).
  • Transmit mode: When BTH is transmitting. BT (DRPb) PM is entirely on.
  • Receive mode: When BTH is receiving. BT (DRPb) PM is entirely on, except for CL1P5 LDO.
  • FM IP Active modes:
  • FM IP OFF/Reset: When Bluetooth is used and FM is not required (BT_EN=H).
  • FM TX: When FM is transmitting. FM (AFE) PM is entirely on.
  • FM RX: When FM is receiving. FM (AFE) PM is entirely on.


There are two failsafe system clocks required for 1271-based modules. Some modules may have both clocks built in, some may have only one of the clocks built in and others may have no clocks built in. The following are recommended for the required clocks when the clock is not built in:

  • REFCLK (AC or DC coupled)

Table 2: Reference Clock Specification

Specification Description
Frequency 26 MHz, 19.2 MHz, 38.4 MHz, 52 MHz (TCXOs) and 38.4 MHz(XTAL)
Accuracy +/- 20 ppm
Type Analog:

Sine wave 200 - 1,200 mVpp (for 11bg)

Sine wave 700 - 1,200 mVpp (for 11a)

Digital: CMOS

Phase Noise -126 dBc/Hz @ 1 KHz for 26 MHz; -141 dBc/Hz @ 100KHz
Duty Cycle 35% - 65%

Table 3: Slow Clock Specification

Specification Description
Frequency 32.768 KHz
Accuracy +/- 150 ppm
Type Digital (CMOS)
Duty Cycle 30% - 70%

Connectivity Example with an OMAP3530 & DM3730 based (1.8V IO) EVMs

This section describes pin connection to an EVM-based application that operates on a 1.8V IO. When the EVM V input/output (IO) is not 1.8 V, a level shifter such as TWL1200 is required to convert the 1.8V IOs of the WLAN to EVM IO voltage.

In this particular example, the WLAN is shown as a daughter board that connects to the OMAP3530/DM3730-based application board.

Solution Hardware-Figure5.jpg

Figure 5: OMAP3530/DM3730-to-WLAN Connectivity - Mistral’s OMAP3530/DM3730 EVM board

The following Table 5a describes how the LSR Module pins should be connected and the actual connection on the Mistral’s OMAP3530/DM3730 EVM board. There should be sufficient ground connection between the WLAN and the OMAP. Ground connections are not shown here.

Table 5a: Pin Connectivity to Mistral’s OMAP3530/DM3730 EVM board

LSR Pin Signal Type Signal Name Connection to OMAP3530/DM3730 EVM Board Mistral EVM Daughter Board Connection Mistral EVM Base Board Expansion Connector
21 Clocks SLOWCLK Connects to a 32 KHz clock. This could come from the power module on board. 32KHz_Exp A53
1 Power VBAT Connects to a (5 - 3.0V) supply (mostly battery). VBAT_Exp A1,A2,B1,B2
6 " VDDS/VIO Connects to a 1.8V supply. (This is the same as VIO.) VIO_1v8 A3,A4,B3,B4
7 Bluetooth - Host I/F BT_EN GPIO on OMAP. T2_LEDSYNC/T2_GPIO13 B5
37 " HCI_RX UART lines on the OMAP. UART2_TX A38
39 " HCI_TX UART lines on the OMAP. UART2_RX A39
3 " BT_UART_WAKE/NC Optional signal. No Connect NC
44 " BT_WAKE_UP Optional signal that can be connected to an OMAP GPIO. MMC2_DAT5 A44
40 Bluetooth Audio AUD_CLK Multi-channel buffered serial port (McBSP) on the OMAP. MCBSP1_CLKX A21
41 " AUD_ DOUT McBSP on the OMAP. MCBSP1_DR A19
43 " AUD_DIN McBSP on the OMAP. MCBSP1_DX A18
45 Bluetooth Debug BT_TX_ DBG PC UART on the board. To USB NC
25 FM - Digital Audio I2S_CLK /NC Optional connection to CODEC interface. McBSP3_CLKX A26
11 " I2S_FYSNC / NC Optional connection to CODEC interface. McBSP3_FSX A29
27 " I2S_DOUT / NC Optional connection to CODEC interface. McBSP3_DX A28
26 " I2S_DIN / NC Optional connection to CODEC interface. McBSP3_DR A27
29 FM Analog Audio FM_AUDL_IN To a microphone/line in connector on the board. Test point NC
34 " FM_AUDIO_PL_OUT To a headset connector on the board. Test point NC
28 " FM_AUDR_IN To a microphone/line in connector on the board. Test point NC
33 " FM_AUDIO_PR_OUT To a headset connector on the board. Test point NC
31 FM Antenna FM_RX_ ANT To an FM antenna on the board. RF connector NC
30 " FM_TX_ ANT To an FM antenna on the board. RF connector NC
6 " WLAN_IRQ Connects to a GPIO for the WLAN IRQ. UART1_RTS/GPIO149 A37
10 WLAN Debug WL_RS232_TX/GPS_TX PC UART connection on the board. To USB NC
9 " WL_RS232_RX/GPS_RX PC UART connection on the board. To USB NC
5 " WL_UART_DBG Connects to a PC-UART line with a jumper configuration. To USB NC

OMAP3530/DM3730-to-WLAN Connectivity - OMAP3530/DM3730 Beagleboard

The following Table 5b describes how the LSR Module pins should be connected and the actual connection on the OMAP3530/DM3730 Beagleboard.

Table 5b: Pin Connectivity to the OMAP3530/DM3730 Beagleboard

LSR Pin Signal Type LSR MOdule Name Beagleboard Expansion Connector Name Beagleboard Coonectivity Usage Beagleboard Expansion Connector Pin
38 Bluetooth - Host I/F HCI_RTS MCBSP3_DX HCI_CTS 4
43 Bluetooth Audio PCM_AUD_IN MCBSP1_DXb* PCM_AUD_OUT 12
15 " SDIO_D3 MMC2_DAT3 SDIO_D3 11
16 " SDIO_D2 MMC2_DAT2 SDIO_D2 13
17 " SDIO_D1 MMC2_DAT1 SDIO_D1 15
18 " SDIO_D0 MMC2_DAT0 SDIO_D0 17
N/A Power N/A VIO_IV8 1V8 1
N/A Power N/A DC_5V_IN 5V 2
N/A N/A No Connect MCBSP1_CLKRb* 20
N/A N/A No Connect MCBSP1_FSRb 22
N/A N/A No Connect I2C2_SDA 23
N/A N/A No Connect I2C2_SCL 24
N/A N/A No Connect REGEN 25
N/A N/A No Connect nRESET 26
N/A N/A No Connect GND GND 27
N/A N/A No Connect GND GND 28
  • Pin MUX Mode 1

High-speed Bus (SDIO) Connectivity

Care should be taken when high-speed signal connections are involved. The bandwidth supported by these lines is not just for the clock frequency, but also for the rise time/fall time requirements.

Table 6 presents the SDIO physical specifications that aid in estimating the bandwidth to be supported by these lines. It is best to have a transmission line impedance that matches when the line length is not classified as a lumped line (l<<λ). The layout of this line can use microstrip or stripline architecture with a trace impedance of ~50 ohms.

Table 6: SDIO Physical Specifications

Parameter Min Max Unit
fclock Clock frequency; CLK CL <= 20 pF 0 26 MHz
DC Low/high duty cycle CL <= 20 pF 40 60 %
tTLH Rise time; CLK CL <= 20 pF 4.3 ns
tTHL Fall time; CLK CL <= 20 pF 3.5 ns
tISU Setup time; input valid before CLK Up CL <= 20 pF 4 ns
tIH Hold time; input valid after CLK Up CL <= 20 pF 5 ns
tODLY Delay time; CLK Down to output valid CL <= 20 pF 2 12 ns

Solution Hardware-Figure6.jpg

Figure 6: SDIO Timing Requirements

Signal Integrity of SDIO Lines

The signal integrity of the SDIO lines is affected by:

  • The line length.
  • The impedance on the line.
  • The impedance discontinuity due to vias or stubs on the lines.
  • Source and/or load matching.

Solution Hardware-Figure7.jpg

Figure 7: Transmission Line from the Driver to the Receiver

If care is not taken to route this correctly, there may be reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape. These signal integrity issues cause failures on SDIO lines.

The SDIO clock is the most sensitive to the signal integrity issues described above. The ringing on this line can cause double-edging problems. Ringing on the clock line causes double-clocking of data. When an OMAP3530 is driving the clock, the clock is sourced (looped) back in from the IO pad, which causes double clock edging if there is ringing on the source side.

Small Line Length

When the line length is low, the ringing is seen on both the source (OMAP side) and the destination (WLAN side). In this case, a series damping resistor is needed to slow the signal and remove the ringing problem. However, the resistor should not be so high that the rise time/fall time requirements are violated. A 33ohm resistor is sufficient.

Long Line Length

When the line length is long, the problem is trickier to handle, as the line must now be treated as the transmission line. If the impedance is not controlled and proper matching is not performed, reflections result. These reflections can have long delays and hence can seriously deform the signal, as show in the figure below:

Solution Hardware-Figure8.jpg

Figure 8: OMAP Long PCB Trace Effect Without Source Matching

In this case, it is important to have either a Microstrip or strip line transmission line implementation. This line should have ~50ohm characteristic impedance. The impedance driven by the OMAP should match the impedance seen through the transmission line, as well as the impedance on the destination side. In some cases, it is difficult to have a well-controlled transmission line routed for these lines, particularly for EVM type application boards. In such cases, there are reflections on the line, due mostly to discontinuity (vias, connectors and so on) on the lines. Nonetheless, the discontinuity on these lines should be minimized and any remaining reflections should be damped on the source side such that any ringing that occurs does not cross the logic thresholds (Vth or Vtl). Installing a series resistor close to the OMAP processor improves the source matching looking to the transmission and also dampens the reflections going back to the OMAP pad.

Solution Hardware-Figure9.jpg

Figure 9: SDIO Clock Signal – 0ohm Series Resistor

Solution Hardware-Figure10.jpg

Figure 10: SDIO Clock Signal – 33ohm Series Resistor

In this example, the slave (accessory) was populated on the expansion connection (similarly to how the WLAN is installed). In this case, since the trace length is long and the reflections can occur from various sources, ringing is seen at the logic threshold levels, which causes spurious clock edges. In this case, a 33ohm instead of a 0ohm resistor was installed close to the OMAP processor on the processor module. This improved the matching looking to the transmission and also dampened the reflections sufficiently, so that the ringing does not occur near the critical thresholds region.

RF Design and Layout Consideration

This section describes the layout that affects the RF performance. In general, the RF lines should be well isolated from the other lines. The solution is built such that the digital IO lines are well isolated from the RF lines. However, there are other lines that cannot be isolated from RF lines.

The power supply lines should have appropriate capacitors placed closed to the pins so that there is no noise sneaking into the IC pads.

Clock Routing

Special care must be taken for the clock trace. Avoid routing these lines below the RF section. They can be routed below or above the ground plane from the RF trace layer (which is generally the top layer).

Slow Clock

The Slow clock is an external crystal oscillator with a frequency of 32.768 KHz. This clock is a square wave clock oscillating from 0 to VIO (1.8V).

There may be significant harmonics due to the nature of this clock. Therefore, this clock should be well isolated so that it does not interfere with the Fast clock and other RF and analog pins and traces.

Crystal Oscillator as the Clock Source

The WL1271/WL1273 oscillator is used with an external crystal in a Colpitts oscillator configuration.

An additional component that is not physically present, but that manifests itself, is Cp, which is the parasitic capacitance of the PCB. The goal of the PCB layout is to minimize Cp. For the best layout, Cp must be as small as possible, because it adds significantly to the overall capacitance when combined with the effective Colpitts capacitance caused by C1 and C2. Also, each crystal has an inherent load capacitance, CL. The goal is a total effective capacitance (including C1/C2/Cp) that matches CL as closely as possible. Note: For a given frequency, select a crystal with the lowest load capacitance (CL).

The layout guidelines are as follows:

  • Ensure that the traces for XTAL are as short as possible. This means that you should place the crystal as close as possible to the WL1251. The board used by TI has an XTAL trace width of 5 mil.
  • Keep all other traces and components, especially the GND traces, as far away as possible from the XTAL traces. In the TI board, the XTAL traces are in the top layer, and the GND traces are in layer 3, separated by two full layers. There is a minimum of 15 mils between XTAL and other traces.

Antenna and Placement

Although the antenna layout should be based on the recommendations of the antenna manufacturer, the guidelines in this section should also be considered.

No Ground beneath Antenna

Ensure that the area below the antenna is free from ground, unless specifically recommended by the antenna manufacturer. This applies to all internal layers.

RF Isolation between WLAN and Other RF Components

When designing the cellular board, place the cellular RF components and antenna according to the following guidelines:

  • Place the WLAN 2.4GHz and 5GHz bands and the cellular RF parts, along with the antennas (GSM or other), as far apart as possible from each other. Keep them on opposite sides of the board.
  • Ensure that the isolation between the WLAN antenna(s) and the other RF antenna is as great as possible.
  • For increased isolation, ensure that the antenna polarizations are orthogonal (90 degrees).
  • Use HPF/LPF circuits to further isolate the WLAN/BT antenna from the other antennas.